Lines Matching refs:lowReg
87 opRegRegImm(cUnit, kOpAdd, rlResult.lowReg, in genNegFloat()
88 rlSrc.lowReg, 0x80000000); in genNegFloat()
100 genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg); in genNegDouble()
125 newLIR3(cUnit, opc, rlDest.lowReg, rlSrc1.lowReg, rlSrc2.lowReg); in withCarryHelper()
148 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlResult.lowReg, rlSrc2.lowReg); in genLong3Addr()
152 rlResult.lowReg, rlSrc2.lowReg); in genLong3Addr()
155 newLIR2(cUnit, kMipsMove, tReg, rlResult.lowReg); in genLong3Addr()
157 tReg, rlResult.lowReg); in genLong3Addr()
165 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlResult.lowReg); in genLong3Addr()
169 rlResult.lowReg, rlSrc1.lowReg); in genLong3Addr()
172 rlSrc1.lowReg, rlResult.lowReg); in genLong3Addr()
180 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg); in genLong3Addr()
184 rlResult.lowReg, rlSrc1.lowReg); in genLong3Addr()
187 rlSrc1.lowReg, rlResult.lowReg); in genLong3Addr()
250 int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg; in genInlinedAbsFloat()
268 int reglo = regSrc.lowReg; in genInlinedAbsDouble()
289 int reg0 = loadValue(cUnit, rlSrc1, kCoreReg).lowReg; in genInlinedMinMaxInt()
290 int reg1 = loadValue(cUnit, rlSrc2, kCoreReg).lowReg; in genInlinedMinMaxInt()
312 opRegRegImm(cUnit, kOpMul, rlResult.lowReg, rlSrc.lowReg, lit); in genMultiplyByTwoBitMultiplier()