132   MachineRegisterInfo *RegInfo = 0;  in ChangeToRegister()  local
136         RegInfo = &MF->getRegInfo();  in ChangeToRegister()
140   if (RegInfo && WasReg)  in ChangeToRegister()
141     RegInfo->removeRegOperandFromUseList(this);  in ChangeToRegister()
163   if (RegInfo)  in ChangeToRegister()
164     RegInfo->addRegOperandToUseList(this);  in ChangeToRegister()
1202                                       const TargetRegisterInfo &RegInfo) {  in substituteRegister()  argument
1205       ToReg = RegInfo.getSubReg(ToReg, SubIdx);  in substituteRegister()
1210       MO.substPhysReg(ToReg, RegInfo);  in substituteRegister()
1217       MO.substVirtReg(ToReg, SubIdx, RegInfo);  in substituteRegister()
1633                                      const TargetRegisterInfo *RegInfo,  in addRegisterKilled()  argument
1637     MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();  in addRegisterKilled()
1662       if (RegInfo->isSuperRegister(IncomingReg, Reg))  in addRegisterKilled()
1664       if (RegInfo->isSubRegister(IncomingReg, Reg))  in addRegisterKilled()
1692                                       const TargetRegisterInfo *RegInfo) {  in clearRegisterKills()  argument
1694     RegInfo = 0;  in clearRegisterKills()
1700     if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))  in clearRegisterKills()
1706                                    const TargetRegisterInfo *RegInfo,  in addRegisterDead()  argument
1710     MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();  in addRegisterDead()
1727       if (RegInfo->isSuperRegister(IncomingReg, Reg))  in addRegisterDead()
1729       if (RegInfo->isSubRegister(IncomingReg, Reg))  in addRegisterDead()
1758                                       const TargetRegisterInfo *RegInfo) {  in addRegisterDefined()  argument
1760     MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);  in addRegisterDefined()