Lines Matching refs:LI
213 const LiveInterval &LI);
215 const LiveInterval &LI);
415 const LiveInterval &LI) { in report() argument
418 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) in report()
419 *OS << PrintReg(LI.reg, TRI); in report()
421 *OS << PrintRegUnit(LI.reg, TRI); in report()
422 *OS << ' ' << LI << '\n'; in report()
426 const LiveInterval &LI) { in report() argument
429 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) in report()
430 *OS << PrintReg(LI.reg, TRI); in report()
432 *OS << PrintRegUnit(LI.reg, TRI); in report()
433 *OS << ' ' << LI << '\n'; in report()
501 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(), in visitMachineBasicBlockBefore() local
503 LI != LE; ++LI) { in visitMachineBasicBlockBefore()
504 unsigned reg = *LI; in visitMachineBasicBlockBefore()
961 LiveInterval &LI = LiveStks->getInterval(MO->getIndex()); in visitMachineOperand() local
963 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) { in visitMachineOperand()
965 *OS << "Live stack: " << LI << '\n'; in visitMachineOperand()
967 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) { in visitMachineOperand()
969 *OS << "Live stack: " << LI << '\n'; in visitMachineOperand()
1004 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(*Units)) { in checkLiveness() local
1005 LiveRangeQuery LRQ(*LI, UseIdx); in checkLiveness()
1009 << ' ' << *LI << '\n'; in checkLiveness()
1013 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LI << '\n'; in checkLiveness()
1022 const LiveInterval &LI = LiveInts->getInterval(Reg); in checkLiveness() local
1023 LiveRangeQuery LRQ(LI, UseIdx); in checkLiveness()
1026 *OS << UseIdx << " is not live in " << LI << '\n'; in checkLiveness()
1032 *OS << "Live range: " << LI << '\n'; in checkLiveness()
1080 const LiveInterval &LI = LiveInts->getInterval(Reg); in checkLiveness() local
1081 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { in checkLiveness()
1086 << DefIdx << " in " << LI << '\n'; in checkLiveness()
1090 *OS << DefIdx << " is not live in " << LI << '\n'; in checkLiveness()
1331 const LiveInterval &LI = LiveInts->getInterval(Reg); in verifyLiveIntervals() local
1332 assert(Reg == LI.reg && "Invalid reg to interval mapping"); in verifyLiveIntervals()
1333 verifyLiveInterval(LI); in verifyLiveIntervals()
1338 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i)) in verifyLiveIntervals() local
1339 verifyLiveInterval(*LI); in verifyLiveIntervals()
1342 void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI, in verifyLiveIntervalValue() argument
1347 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def); in verifyLiveIntervalValue()
1350 report("Valno not live at def and not marked unused", MF, LI); in verifyLiveIntervalValue()
1356 report("Live range at def has different valno", MF, LI); in verifyLiveIntervalValue()
1364 report("Invalid definition index", MF, LI); in verifyLiveIntervalValue()
1366 << " in " << LI << '\n'; in verifyLiveIntervalValue()
1372 report("PHIDef value is not defined at MBB start", MBB, LI); in verifyLiveIntervalValue()
1382 report("No instruction at def index", MBB, LI); in verifyLiveIntervalValue()
1392 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { in verifyLiveIntervalValue()
1393 if (MOI->getReg() != LI.reg) in verifyLiveIntervalValue()
1397 !TRI->hasRegUnit(MOI->getReg(), LI.reg)) in verifyLiveIntervalValue()
1407 *OS << "Valno #" << VNI->id << " in " << LI << '\n'; in verifyLiveIntervalValue()
1414 report("Early clobber def must be at an early-clobber slot", MBB, LI); in verifyLiveIntervalValue()
1419 MBB, LI); in verifyLiveIntervalValue()
1425 MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI, in verifyLiveIntervalSegment() argument
1430 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) { in verifyLiveIntervalSegment()
1431 report("Foreign valno in live range", MF, LI); in verifyLiveIntervalSegment()
1436 report("Live range valno is marked unused", MF, LI); in verifyLiveIntervalSegment()
1442 report("Bad start of live segment, no basic block", MF, LI); in verifyLiveIntervalSegment()
1448 report("Live segment must begin at MBB entry or valno def", MBB, LI); in verifyLiveIntervalSegment()
1455 report("Bad end of live segment, no basic block", MF, LI); in verifyLiveIntervalSegment()
1465 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() && in verifyLiveIntervalSegment()
1473 report("Live segment doesn't end at a valid instruction", EndMBB, LI); in verifyLiveIntervalSegment()
1480 report("Live segment ends at B slot of an instruction", EndMBB, LI); in verifyLiveIntervalSegment()
1488 report("Live segment ending at dead slot spans instructions", EndMBB, LI); in verifyLiveIntervalSegment()
1496 if (I+1 == LI.end() || (I+1)->start != I->end) { in verifyLiveIntervalSegment()
1498 "redefined by an EC def in the same instruction", EndMBB, LI); in verifyLiveIntervalSegment()
1505 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { in verifyLiveIntervalSegment()
1511 if (!MOI->isReg() || MOI->getReg() != LI.reg) in verifyLiveIntervalSegment()
1523 *OS << " in " << LI << '\n'; in verifyLiveIntervalSegment()
1528 *OS << *I << " in " << LI << '\n'; in verifyLiveIntervalSegment()
1544 assert(LiveInts->isLiveInToMBB(LI, MFI)); in verifyLiveIntervalSegment()
1546 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && in verifyLiveIntervalSegment()
1562 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd); in verifyLiveIntervalSegment()
1566 report("Register not marked live out of predecessor", *PI, LI); in verifyLiveIntervalSegment()
1575 report("Different value live out of predecessor", *PI, LI); in verifyLiveIntervalSegment()
1588 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) { in verifyLiveInterval() argument
1589 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end(); in verifyLiveInterval()
1591 verifyLiveIntervalValue(LI, *I); in verifyLiveInterval()
1593 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) in verifyLiveInterval()
1594 verifyLiveIntervalSegment(LI, I); in verifyLiveInterval()
1597 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { in verifyLiveInterval()
1599 unsigned NumComp = ConEQ.Classify(&LI); in verifyLiveInterval()
1601 report("Multiple connected components in live interval", MF, LI); in verifyLiveInterval()
1604 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), in verifyLiveInterval()
1605 E = LI.vni_end(); I!=E; ++I) in verifyLiveInterval()