Lines Matching refs:SubIdx
424 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
427 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
440 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
475 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
484 SubIdx == DefSubIdx && in EmitSubregNode()
499 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
509 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
516 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
533 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
554 MIB.addImm(SubIdx); in EmitSubregNode()
608 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
612 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()