Lines Matching refs:MIB
672 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg() local
673 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
675 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
676 AddDefaultPred(MIB); in copyPhysReg()
745 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg() argument
749 return MIB.addReg(Reg, State); in AddDReg()
752 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddDReg()
753 return MIB.addReg(Reg, State, SubIdx); in AddDReg()
793 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); in storeRegToStackSlot() local
794 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
795 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
796 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); in storeRegToStackSlot()
798 AddDefaultPred(MIB); in storeRegToStackSlot()
802 MachineInstrBuilder MIB = in storeRegToStackSlot() local
805 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
806 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
837 MachineInstrBuilder MIB = in storeRegToStackSlot() local
841 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
842 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
843 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
858 MachineInstrBuilder MIB = in storeRegToStackSlot() local
862 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
863 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
864 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
865 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
872 MachineInstrBuilder MIB = in storeRegToStackSlot() local
876 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
877 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
878 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
879 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
880 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
881 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
882 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
883 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
981 MachineInstrBuilder MIB; in loadRegFromStackSlot() local
984 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
985 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
986 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
987 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
989 AddDefaultPred(MIB); in loadRegFromStackSlot()
993 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
995 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
996 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1000 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1025 MachineInstrBuilder MIB = in loadRegFromStackSlot() local
1029 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1030 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1031 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1033 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1045 MachineInstrBuilder MIB = in loadRegFromStackSlot() local
1049 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1050 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1051 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1052 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1054 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1061 MachineInstrBuilder MIB = in loadRegFromStackSlot() local
1065 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1066 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1067 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1068 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1069 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1070 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1071 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1072 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1074 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1173 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in expandPostRAPseudo() local
1185 AddDefaultPred(MIB); in expandPostRAPseudo()
1192 MIB.addReg(SrcRegS, RegState::Implicit); in expandPostRAPseudo()
1268 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), in reMaterialize() local
1271 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); in reMaterialize()
3828 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in setExecutionDomain() local
3850 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) in setExecutionDomain()
3872 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) in setExecutionDomain()
3878 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
3901 MIB.addReg(DReg, RegState::Define) in setExecutionDomain()
3905 AddDefaultPred(MIB); in setExecutionDomain()
3909 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); in setExecutionDomain()
3911 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
3937 MIB.addReg(DDst, RegState::Define) in setExecutionDomain()
3940 AddDefaultPred(MIB); in setExecutionDomain()
3944 MIB.addReg(DstReg, RegState::Implicit | RegState::Define); in setExecutionDomain()
3945 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
3947 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
3985 MIB.addReg(DDst, RegState::Define); in setExecutionDomain()
3991 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
3995 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
3997 MIB.addImm(1); in setExecutionDomain()
3998 AddDefaultPred(MIB); in setExecutionDomain()
4001 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4005 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); in setExecutionDomain()
4007 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()