Lines Matching refs:MIB
383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
400 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
404 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
417 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MO); in ExpandVLD()
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
429 TransferImpOps(MI, MIB, MIB); in ExpandVLD()
432 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVLD()
448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST() local
452 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
455 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
456 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
459 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
466 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
468 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
470 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
472 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
475 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
476 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
479 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandVST()
480 TransferImpOps(MI, MIB, MIB); in ExpandVST()
483 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVST()
500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp() local
522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
524 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
526 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
528 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
532 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
535 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
536 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
539 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
549 MIB.addReg(D0, SrcFlags); in ExpandLaneOp()
551 MIB.addReg(D1, SrcFlags); in ExpandLaneOp()
553 MIB.addReg(D2, SrcFlags); in ExpandLaneOp()
555 MIB.addReg(D3, SrcFlags); in ExpandLaneOp()
558 MIB.addImm(Lane); in ExpandLaneOp()
562 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
563 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
567 MIB.addOperand(MO); in ExpandLaneOp()
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
571 TransferImpOps(MI, MIB, MIB); in ExpandLaneOp()
573 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandLaneOp()
584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL() local
588 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
590 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
596 MIB.addReg(D0); in ExpandVTBL()
599 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
602 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
603 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
606 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandVTBL()
607 TransferImpOps(MI, MIB, MIB); in ExpandVTBL()
839 MachineInstrBuilder MIB = in ExpandMI() local
845 TransferImpOps(MI, MIB, MIB); in ExpandMI()
851 MachineInstrBuilder MIB = in ExpandMI() local
856 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
857 TransferImpOps(MI, MIB, MIB); in ExpandMI()
943 MachineInstrBuilder MIB = in ExpandMI() local
952 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
955 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
956 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
961 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
965 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
966 TransferImpOps(MI, MIB, MIB); in ExpandMI()
967 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
974 MachineInstrBuilder MIB = in ExpandMI() local
983 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
986 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
987 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
992 MIB.addReg(D0).addReg(D1); in ExpandMI()
995 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandMI()
997 TransferImpOps(MI, MIB, MIB); in ExpandMI()
998 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
1006 MachineInstrBuilder MIB = in ExpandMI() local
1016 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1017 MIB.addReg(DReg); in ExpandMI()
1020 MIB.addImm(Lane); in ExpandMI()
1022 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1023 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1025 TransferImpOps(MI, MIB, MIB); in ExpandMI()