Lines Matching refs:NewOpc
2575 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local
2577 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
5509 unsigned NewOpc = 0; in LowerMUL() local
5514 NewOpc = ARMISD::VMULLs; in LowerMUL()
5519 NewOpc = ARMISD::VMULLu; in LowerMUL()
5524 NewOpc = ARMISD::VMULLs; in LowerMUL()
5527 NewOpc = ARMISD::VMULLu; in LowerMUL()
5531 NewOpc = ARMISD::VMULLu; in LowerMUL()
5536 if (!NewOpc) { in LowerMUL()
5555 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
5570 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
5572 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
7337 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? in EmitInstrWithCustomInserter() local
7347 BuildMI(*BB, MI, dl, TII->get(NewOpc)) in EmitInstrWithCustomInserter()
7361 unsigned NewOpc; in EmitInstrWithCustomInserter() local
7364 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; in EmitInstrWithCustomInserter()
7365 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; in EmitInstrWithCustomInserter()
7366 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; in EmitInstrWithCustomInserter()
7368 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); in EmitInstrWithCustomInserter()
7704 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); in AdjustInstrPostInstrSelection() local
7705 if (NewOpc) { in AdjustInstrPostInstrSelection()
7708 MCID = &TII->get(NewOpc); in AdjustInstrPostInstrSelection()
7723 assert(!NewOpc && "Optional cc_out operand required"); in AdjustInstrPostInstrSelection()
7742 assert(!NewOpc && "Optional cc_out operand required"); in AdjustInstrPostInstrSelection()
9042 unsigned NewOpc = 0; in CombineBaseUpdate() local
9048 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; in CombineBaseUpdate()
9050 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; in CombineBaseUpdate()
9052 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; in CombineBaseUpdate()
9054 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; in CombineBaseUpdate()
9056 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; in CombineBaseUpdate()
9058 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; in CombineBaseUpdate()
9060 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; in CombineBaseUpdate()
9062 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; in CombineBaseUpdate()
9064 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; in CombineBaseUpdate()
9066 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; in CombineBaseUpdate()
9068 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; in CombineBaseUpdate()
9070 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; in CombineBaseUpdate()
9072 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; in CombineBaseUpdate()
9074 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; in CombineBaseUpdate()
9081 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; in CombineBaseUpdate()
9082 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
9083 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
9126 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, in CombineBaseUpdate()
9161 unsigned NewOpc = 0; in CombineVLDDUP() local
9165 NewOpc = ARMISD::VLD2DUP; in CombineVLDDUP()
9168 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
9171 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
9200 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, in CombineVLDDUP()