Lines Matching refs:VA
1289 CCValAssign VA = RVLocs[i]; in LowerCallResult() local
1294 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
1301 if (VA.needsCustom()) { in LowerCallResult()
1303 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1307 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1308 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1314 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1319 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1320 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1323 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1324 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1332 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1338 switch (VA.getLocInfo()) { in LowerCallResult()
1342 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1357 const CCValAssign &VA, in LowerMemOpCallTo() argument
1359 unsigned LocMemOffset = VA.getLocMemOffset(); in LowerMemOpCallTo()
1370 CCValAssign &VA, CCValAssign &NextVA, in PassF64ArgInRegs() argument
1377 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); in PassF64ArgInRegs()
1461 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
1467 switch (VA.getLocInfo()) { in LowerCall()
1471 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1474 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1477 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1480 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1485 if (VA.needsCustom()) { in LowerCall()
1486 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
1493 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1495 VA = ArgLocs[++i]; // skip ahead to next loc in LowerCall()
1496 if (VA.isRegLoc()) { in LowerCall()
1498 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1500 assert(VA.isMemLoc()); in LowerCall()
1503 dl, DAG, VA, Flags)); in LowerCall()
1506 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], in LowerCall()
1509 } else if (VA.isRegLoc()) { in LowerCall()
1511 assert(VA.getLocVT() == MVT::i32 && in LowerCall()
1517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1519 assert(VA.isMemLoc()); in LowerCall()
1552 unsigned LocMemOffset = VA.getLocMemOffset(); in LowerCall()
1568 assert(VA.isMemLoc()); in LowerCall()
1571 dl, DAG, VA, Flags)); in LowerCall()
2020 CCValAssign &VA = ArgLocs[i]; in IsEligibleForTailCallOptimization() local
2021 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization()
2024 if (VA.getLocInfo() == CCValAssign::Indirect) in IsEligibleForTailCallOptimization()
2026 if (VA.needsCustom()) { in IsEligibleForTailCallOptimization()
2031 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2041 } else if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
2042 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, in IsEligibleForTailCallOptimization()
2090 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
2091 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
2095 switch (VA.getLocInfo()) { in LowerReturn()
2099 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2103 if (VA.needsCustom()) { in LowerReturn()
2104 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
2111 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); in LowerReturn()
2113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2114 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2115 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2118 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2119 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2129 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); in LowerReturn()
2131 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2132 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2133 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), in LowerReturn()
2136 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
2141 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2653 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, in GetF64FormalArgument() argument
2666 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in GetF64FormalArgument()
2888 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
2889 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx); in LowerFormalArguments()
2890 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex; in LowerFormalArguments()
2892 if (VA.isRegLoc()) { in LowerFormalArguments()
2893 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
2895 if (VA.needsCustom()) { in LowerFormalArguments()
2898 if (VA.getLocVT() == MVT::v2f64) { in LowerFormalArguments()
2899 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
2901 VA = ArgLocs[++i]; // skip ahead to next loc in LowerFormalArguments()
2903 if (VA.isMemLoc()) { in LowerFormalArguments()
2904 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); in LowerFormalArguments()
2910 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
2919 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); in LowerFormalArguments()
2938 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
2945 switch (VA.getLocInfo()) { in LowerFormalArguments()
2949 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
2953 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
2954 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
2958 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
2959 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
2968 assert(VA.isMemLoc()); in LowerFormalArguments()
2969 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); in LowerFormalArguments()
2988 Ins[VA.getValNo()].PartOffset, in LowerFormalArguments()
2989 VA.getLocMemOffset(), in LowerFormalArguments()
2995 unsigned FIOffset = VA.getLocMemOffset() + in LowerFormalArguments()
2997 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, in LowerFormalArguments()
3002 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, in LowerFormalArguments()