Lines Matching refs:N2RegVShLFrm

2995            (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3701 //   with f of either N2RegVShLFrm or N2RegVShRFrm
3707   def v8i8  : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3711   def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3715   def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3719   def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3724   def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3728   def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3732   def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3736   def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3818 //   with f of either N2RegVShLFrm or N2RegVShRFrm
3824                         N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3828                         N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3832                         N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3836                         N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3841                         N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3845                         N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3849                         N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3853                         N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;