Lines Matching refs:v4i32
1030 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1325 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1980 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2022 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
3113 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3116 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3120 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3145 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3146 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3161 v4i16, v4i32, OpNode>;
3178 v4i16, v4i32, IntOp>;
3191 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3192 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3224 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3226 v4i32, v4i32, OpNode, Commutable>;
3233 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3234 v4i32, v2i32, ShOp>;
3273 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3275 v4i32, v4i32, IntOp, Commutable>;
3294 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3296 v4i32, v4i32, IntOp>;
3309 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3310 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3384 v4i16, v4i32, IntOp, Commutable>;
3400 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3402 v4i32, v4i16, OpNode, Commutable>;
3412 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3424 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3426 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3439 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3441 v4i32, v4i16, IntOp, Commutable>;
3451 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3475 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3477 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3492 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3494 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3520 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3521 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3535 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3536 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3559 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3560 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3581 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3582 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3594 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3595 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3603 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3615 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3616 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3624 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3645 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3646 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3671 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3672 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3673 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3694 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3695 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3696 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3732 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3733 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3769 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3770 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3808 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3809 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3848 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3849 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3884 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3885 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3901 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3902 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3923 v4i16, v4i32, shr_imm16, OpNode> {
4006 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4007 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4008 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4033 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4034 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4036 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4055 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4056 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4058 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4107 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4108 (mul (v4i32 QPR:$src2),
4109 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4110 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4165 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4166 (mul (v4i32 QPR:$src2),
4167 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4168 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4272 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4286 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4303 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4317 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4322 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4357 v4i32, v4i32, and, 1>;
4363 v4i32, v4i32, xor, 1>;
4369 v4i32, v4i32, or, 1>;
4403 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4418 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4454 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4467 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4498 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4511 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4513 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4558 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4568 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4569 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4581 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4776 v4i32, v4i32, int_arm_neon_vrecpe>;
4798 v4i32, v4i32, int_arm_neon_vrsqrte>;
4849 v4i32, v4i16, imm16, NEONvshlli>;
4953 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
4954 (v4i32 (bitconvert (v16i8 (add QPR:$src,
4957 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
4958 (v4i32 (bitconvert (v8i16 (add QPR:$src,
4961 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
4962 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
4978 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4995 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5012 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5091 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5173 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5182 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5237 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5238 (v4i32 (INSERT_SUBREG QPR:$src1,
5278 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5279 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5300 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5350 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5369 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5370 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5397 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5413 v4i32, v4f32, fp_to_sint>;
5415 v4i32, v4f32, fp_to_uint>;
5417 v4f32, v4i32, sint_to_fp>;
5419 v4f32, v4i32, uint_to_fp>;
5428 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5432 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5455 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5457 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5459 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5461 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5496 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5546 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5603 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5839 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5844 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5845 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5846 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5847 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5848 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5850 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5855 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5860 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5865 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5930 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
5998 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6004 // Double lengthening - v4i8 -> v4i16 -> v4i32