776   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);  in MergeBaseUpdateLSMultiple()  local
777   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))  in MergeBaseUpdateLSMultiple()
875   unsigned NewOpc = 0;  in MergeBaseUpdateLoadStore()  local
893       NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);  in MergeBaseUpdateLoadStore()
912       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);  in MergeBaseUpdateLoadStore()
930     BuildMI(MBB, MBBI, dl, TII->get(NewOpc))  in MergeBaseUpdateLoadStore()
939       if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {  in MergeBaseUpdateLoadStore()
941         BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())  in MergeBaseUpdateLoadStore()
946         BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())  in MergeBaseUpdateLoadStore()
953       BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())  in MergeBaseUpdateLoadStore()
962     if (isAM2 && NewOpc == ARM::STR_POST_IMM) {  in MergeBaseUpdateLoadStore()
965       BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)  in MergeBaseUpdateLoadStore()
971       BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)  in MergeBaseUpdateLoadStore()
1075                           DebugLoc dl, unsigned NewOpc,  in InsertLDR_STR()  argument
1083                                       TII->get(NewOpc))  in InsertLDR_STR()
1089                                       TII->get(NewOpc))  in InsertLDR_STR()
1135       unsigned NewOpc = (isLd)  in FixInvalidRegPairOp()  local
1139         BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))  in FixInvalidRegPairOp()
1146         BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))  in FixInvalidRegPairOp()
1158       unsigned NewOpc = (isLd)  in FixInvalidRegPairOp()  local
1178         InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,  in FixInvalidRegPairOp()
1193         InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,  in FixInvalidRegPairOp()
1421       unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);  in MergeReturnIntoLDM()  local
1424       PrevMI->setDesc(TII->get(NewOpc));  in MergeReturnIntoLDM()
1481                           unsigned &NewOpc, unsigned &EvenReg,
1577                                           unsigned &NewOpc, unsigned &EvenReg,  in CanFormLdStDWord()  argument
1590     NewOpc = ARM::LDRD;  in CanFormLdStDWord()
1592     NewOpc = ARM::STRD;  in CanFormLdStDWord()
1594     NewOpc = ARM::t2LDRDi8;  in CanFormLdStDWord()
1598     NewOpc = ARM::t2STRDi8;  in CanFormLdStDWord()
1744         unsigned NewOpc = 0;  in RescheduleOps()  local
1747         if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,  in RescheduleOps()
1753           const MCInstrDesc &MCID = TII->get(NewOpc);  in RescheduleOps()