Lines Matching refs:Inst
222 void cvtThumbMultiply(MCInst &Inst,
224 bool validateInstruction(MCInst &Inst,
226 bool processInstruction(MCInst &Inst,
232 bool isDeprecated(MCInst &Inst, StringRef &Info);
274 unsigned checkTargetMatchPredicate(MCInst &Inst);
1485 void addExpr(MCInst &Inst, const MCExpr *Expr) const { in addExpr() argument
1488 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
1490 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
1492 Inst.addOperand(MCOperand::CreateExpr(Expr)); in addExpr()
1495 void addCondCodeOperands(MCInst &Inst, unsigned N) const { in addCondCodeOperands() argument
1497 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
1499 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1502 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { in addCoprocNumOperands() argument
1504 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocNumOperands()
1507 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { in addCoprocRegOperands() argument
1509 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocRegOperands()
1512 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { in addCoprocOptionOperands() argument
1514 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); in addCoprocOptionOperands()
1517 void addITMaskOperands(MCInst &Inst, unsigned N) const { in addITMaskOperands() argument
1519 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); in addITMaskOperands()
1522 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { in addITCondCodeOperands() argument
1524 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addITCondCodeOperands()
1527 void addCCOutOperands(MCInst &Inst, unsigned N) const { in addCCOutOperands() argument
1529 Inst.addOperand(MCOperand::CreateReg(getReg())); in addCCOutOperands()
1532 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() argument
1534 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
1537 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { in addRegShiftedRegOperands() argument
1541 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
1542 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
1543 Inst.addOperand(MCOperand::CreateImm( in addRegShiftedRegOperands()
1547 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { in addRegShiftedImmOperands() argument
1551 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
1554 Inst.addOperand(MCOperand::CreateImm( in addRegShiftedImmOperands()
1558 void addShifterImmOperands(MCInst &Inst, unsigned N) const { in addShifterImmOperands() argument
1560 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | in addShifterImmOperands()
1564 void addRegListOperands(MCInst &Inst, unsigned N) const { in addRegListOperands() argument
1569 Inst.addOperand(MCOperand::CreateReg(*I)); in addRegListOperands()
1572 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { in addDPRRegListOperands() argument
1573 addRegListOperands(Inst, N); in addDPRRegListOperands()
1576 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { in addSPRRegListOperands() argument
1577 addRegListOperands(Inst, N); in addSPRRegListOperands()
1580 void addRotImmOperands(MCInst &Inst, unsigned N) const { in addRotImmOperands() argument
1583 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); in addRotImmOperands()
1586 void addBitfieldOperands(MCInst &Inst, unsigned N) const { in addBitfieldOperands() argument
1594 Inst.addOperand(MCOperand::CreateImm(Mask)); in addBitfieldOperands()
1597 void addImmOperands(MCInst &Inst, unsigned N) const { in addImmOperands() argument
1599 addExpr(Inst, getImm()); in addImmOperands()
1602 void addFBits16Operands(MCInst &Inst, unsigned N) const { in addFBits16Operands() argument
1605 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); in addFBits16Operands()
1608 void addFBits32Operands(MCInst &Inst, unsigned N) const { in addFBits32Operands() argument
1611 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); in addFBits32Operands()
1614 void addFPImmOperands(MCInst &Inst, unsigned N) const { in addFPImmOperands() argument
1618 Inst.addOperand(MCOperand::CreateImm(Val)); in addFPImmOperands()
1621 void addImm8s4Operands(MCInst &Inst, unsigned N) const { in addImm8s4Operands() argument
1626 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addImm8s4Operands()
1629 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { in addImm0_1020s4Operands() argument
1634 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); in addImm0_1020s4Operands()
1637 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { in addImm0_508s4NegOperands() argument
1642 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); in addImm0_508s4NegOperands()
1645 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { in addImm0_508s4Operands() argument
1650 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); in addImm0_508s4Operands()
1653 void addImm1_16Operands(MCInst &Inst, unsigned N) const { in addImm1_16Operands() argument
1658 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); in addImm1_16Operands()
1661 void addImm1_32Operands(MCInst &Inst, unsigned N) const { in addImm1_32Operands() argument
1666 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); in addImm1_32Operands()
1669 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { in addImmThumbSROperands() argument
1675 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); in addImmThumbSROperands()
1678 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { in addPKHASRImmOperands() argument
1684 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); in addPKHASRImmOperands()
1687 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { in addT2SOImmNotOperands() argument
1692 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); in addT2SOImmNotOperands()
1695 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { in addT2SOImmNegOperands() argument
1700 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); in addT2SOImmNegOperands()
1703 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { in addImm0_4095NegOperands() argument
1708 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); in addImm0_4095NegOperands()
1711 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { in addUnsignedOffset_b8s2Operands() argument
1713 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); in addUnsignedOffset_b8s2Operands()
1719 Inst.addOperand(MCOperand::CreateExpr(SR)); in addUnsignedOffset_b8s2Operands()
1722 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { in addThumbMemPCOperands() argument
1727 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addThumbMemPCOperands()
1733 Inst.addOperand(MCOperand::CreateExpr(SR)); in addThumbMemPCOperands()
1739 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); in addThumbMemPCOperands()
1742 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { in addARMSOImmNotOperands() argument
1747 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); in addARMSOImmNotOperands()
1750 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { in addARMSOImmNegOperands() argument
1755 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); in addARMSOImmNegOperands()
1758 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { in addMemBarrierOptOperands() argument
1760 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); in addMemBarrierOptOperands()
1763 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { in addInstSyncBarrierOptOperands() argument
1765 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); in addInstSyncBarrierOptOperands()
1768 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { in addMemNoOffsetOperands() argument
1770 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
1773 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { in addMemPCRelImm12Operands() argument
1778 Inst.addOperand(MCOperand::CreateImm(Imm)); in addMemPCRelImm12Operands()
1781 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { in addAdrLabelOperands() argument
1788 Inst.addOperand(MCOperand::CreateExpr(getImm())); in addAdrLabelOperands()
1794 Inst.addOperand(MCOperand::CreateImm(Val)); in addAdrLabelOperands()
1797 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { in addAlignedMemoryOperands() argument
1799 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
1800 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); in addAlignedMemoryOperands()
1803 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { in addAddrMode2Operands() argument
1818 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAddrMode2Operands()
1819 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); in addAddrMode2Operands()
1820 Inst.addOperand(MCOperand::CreateImm(Val)); in addAddrMode2Operands()
1823 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { in addAM2OffsetImmOperands() argument
1833 Inst.addOperand(MCOperand::CreateReg(0)); in addAM2OffsetImmOperands()
1834 Inst.addOperand(MCOperand::CreateImm(Val)); in addAM2OffsetImmOperands()
1837 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { in addAddrMode3Operands() argument
1843 Inst.addOperand(MCOperand::CreateExpr(getImm())); in addAddrMode3Operands()
1844 Inst.addOperand(MCOperand::CreateReg(0)); in addAddrMode3Operands()
1845 Inst.addOperand(MCOperand::CreateImm(0)); in addAddrMode3Operands()
1861 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAddrMode3Operands()
1862 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); in addAddrMode3Operands()
1863 Inst.addOperand(MCOperand::CreateImm(Val)); in addAddrMode3Operands()
1866 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { in addAM3OffsetOperands() argument
1871 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
1872 Inst.addOperand(MCOperand::CreateImm(Val)); in addAM3OffsetOperands()
1884 Inst.addOperand(MCOperand::CreateReg(0)); in addAM3OffsetOperands()
1885 Inst.addOperand(MCOperand::CreateImm(Val)); in addAM3OffsetOperands()
1888 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { in addAddrMode5Operands() argument
1894 Inst.addOperand(MCOperand::CreateExpr(getImm())); in addAddrMode5Operands()
1895 Inst.addOperand(MCOperand::CreateImm(0)); in addAddrMode5Operands()
1906 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAddrMode5Operands()
1907 Inst.addOperand(MCOperand::CreateImm(Val)); in addAddrMode5Operands()
1910 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm8s4OffsetOperands() argument
1916 Inst.addOperand(MCOperand::CreateExpr(getImm())); in addMemImm8s4OffsetOperands()
1917 Inst.addOperand(MCOperand::CreateImm(0)); in addMemImm8s4OffsetOperands()
1922 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemImm8s4OffsetOperands()
1923 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemImm8s4OffsetOperands()
1926 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm0_1020s4OffsetOperands() argument
1930 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemImm0_1020s4OffsetOperands()
1931 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemImm0_1020s4OffsetOperands()
1934 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm8OffsetOperands() argument
1937 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemImm8OffsetOperands()
1938 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemImm8OffsetOperands()
1941 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { in addMemPosImm8OffsetOperands() argument
1942 addMemImm8OffsetOperands(Inst, N); in addMemPosImm8OffsetOperands()
1945 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { in addMemNegImm8OffsetOperands() argument
1946 addMemImm8OffsetOperands(Inst, N); in addMemNegImm8OffsetOperands()
1949 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { in addMemUImm12OffsetOperands() argument
1953 addExpr(Inst, getImm()); in addMemUImm12OffsetOperands()
1954 Inst.addOperand(MCOperand::CreateImm(0)); in addMemUImm12OffsetOperands()
1960 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemUImm12OffsetOperands()
1961 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemUImm12OffsetOperands()
1964 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm12OffsetOperands() argument
1968 addExpr(Inst, getImm()); in addMemImm12OffsetOperands()
1969 Inst.addOperand(MCOperand::CreateImm(0)); in addMemImm12OffsetOperands()
1975 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemImm12OffsetOperands()
1976 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemImm12OffsetOperands()
1979 void addMemTBBOperands(MCInst &Inst, unsigned N) const { in addMemTBBOperands() argument
1981 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemTBBOperands()
1982 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); in addMemTBBOperands()
1985 void addMemTBHOperands(MCInst &Inst, unsigned N) const { in addMemTBHOperands() argument
1987 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemTBHOperands()
1988 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); in addMemTBHOperands()
1991 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { in addMemRegOffsetOperands() argument
1996 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemRegOffsetOperands()
1997 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); in addMemRegOffsetOperands()
1998 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemRegOffsetOperands()
2001 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { in addT2MemRegOffsetOperands() argument
2003 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addT2MemRegOffsetOperands()
2004 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); in addT2MemRegOffsetOperands()
2005 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); in addT2MemRegOffsetOperands()
2008 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { in addMemThumbRROperands() argument
2010 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemThumbRROperands()
2011 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); in addMemThumbRROperands()
2014 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { in addMemThumbRIs4Operands() argument
2017 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemThumbRIs4Operands()
2018 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemThumbRIs4Operands()
2021 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { in addMemThumbRIs2Operands() argument
2024 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemThumbRIs2Operands()
2025 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemThumbRIs2Operands()
2028 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { in addMemThumbRIs1Operands() argument
2031 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemThumbRIs1Operands()
2032 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemThumbRIs1Operands()
2035 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { in addMemThumbSPIOperands() argument
2038 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemThumbSPIOperands()
2039 Inst.addOperand(MCOperand::CreateImm(Val)); in addMemThumbSPIOperands()
2042 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { in addPostIdxImm8Operands() argument
2050 Inst.addOperand(MCOperand::CreateImm(Imm)); in addPostIdxImm8Operands()
2053 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { in addPostIdxImm8s4Operands() argument
2062 Inst.addOperand(MCOperand::CreateImm(Imm)); in addPostIdxImm8s4Operands()
2065 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { in addPostIdxRegOperands() argument
2067 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addPostIdxRegOperands()
2068 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
2071 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { in addPostIdxRegShiftedOperands() argument
2073 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addPostIdxRegShiftedOperands()
2079 Inst.addOperand(MCOperand::CreateImm(Imm)); in addPostIdxRegShiftedOperands()
2082 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { in addMSRMaskOperands() argument
2084 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); in addMSRMaskOperands()
2087 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { in addProcIFlagsOperands() argument
2089 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); in addProcIFlagsOperands()
2092 void addVecListOperands(MCInst &Inst, unsigned N) const { in addVecListOperands() argument
2094 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); in addVecListOperands()
2097 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { in addVecListIndexedOperands() argument
2099 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); in addVecListIndexedOperands()
2100 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); in addVecListIndexedOperands()
2103 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { in addVectorIndex8Operands() argument
2105 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); in addVectorIndex8Operands()
2108 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { in addVectorIndex16Operands() argument
2110 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); in addVectorIndex16Operands()
2113 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { in addVectorIndex32Operands() argument
2115 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); in addVectorIndex32Operands()
2118 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { in addNEONi8splatOperands() argument
2123 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); in addNEONi8splatOperands()
2126 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { in addNEONi16splatOperands() argument
2135 Inst.addOperand(MCOperand::CreateImm(Value)); in addNEONi16splatOperands()
2138 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { in addNEONi32splatOperands() argument
2149 Inst.addOperand(MCOperand::CreateImm(Value)); in addNEONi32splatOperands()
2152 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { in addNEONi32vmovOperands() argument
2163 Inst.addOperand(MCOperand::CreateImm(Value)); in addNEONi32vmovOperands()
2166 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { in addNEONi32vmovNegOperands() argument
2177 Inst.addOperand(MCOperand::CreateImm(Value)); in addNEONi32vmovNegOperands()
2180 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { in addNEONi64splatOperands() argument
2189 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); in addNEONi64splatOperands()
4089 cvtThumbMultiply(MCInst &Inst, in cvtThumbMultiply() argument
4091 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); in cvtThumbMultiply()
4092 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); in cvtThumbMultiply()
4100 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); in cvtThumbMultiply()
4101 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
4102 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); in cvtThumbMultiply()
4880 bool ARMAsmParser::isDeprecated(MCInst &Inst, StringRef &Info) { in isDeprecated() argument
4881 if (hasV8Ops() && Inst.getOpcode() == ARM::SETEND) { in isDeprecated()
5178 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, in checkLowRegisterList() argument
5181 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { in checkLowRegisterList()
5182 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList()
5194 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { in listContainsReg() argument
5195 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { in listContainsReg()
5196 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg()
5215 validateInstruction(MCInst &Inst, in validateInstruction() argument
5217 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); in validateInstruction()
5223 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && in validateInstruction()
5224 Inst.getOpcode() != ARM::BKPT) { in validateInstruction()
5233 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); in validateInstruction()
5249 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != in validateInstruction()
5250 ARMCC::AL && Inst.getOpcode() != ARM::tB && in validateInstruction()
5251 Inst.getOpcode() != ARM::t2B) in validateInstruction()
5254 switch (Inst.getOpcode()) { in validateInstruction()
5259 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
5260 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
5268 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
5269 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
5278 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
5279 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction()
5288 unsigned lsb = Inst.getOperand(2).getImm(); in validateInstruction()
5289 unsigned widthm1 = Inst.getOperand(3).getImm(); in validateInstruction()
5303 unsigned Rn = Inst.getOperand(0).getReg(); in validateInstruction()
5308 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) in validateInstruction()
5325 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) in validateInstruction()
5355 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && in validateInstruction()
5363 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && in validateInstruction()
5371 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) in validateInstruction()
5380 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in validateInstruction()
5389 if (isDeprecated(Inst, DepInfo)) in validateInstruction()
5652 processInstruction(MCInst &Inst, in processInstruction() argument
5654 switch (Inst.getOpcode()) { in processInstruction()
5657 if (Inst.getOperand(1).getReg() != ARM::PC || in processInstruction()
5658 Inst.getOperand(5).getReg() != 0) in processInstruction()
5662 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
5663 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
5664 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
5665 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
5666 Inst = TmpInst; in processInstruction()
5672 if (Inst.getOperand(1).getImm() > 0 && in processInstruction()
5673 Inst.getOperand(1).getImm() <= 0xff && in processInstruction()
5676 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
5678 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
5681 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
5684 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
5687 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
5690 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
5700 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5701 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5702 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5703 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5704 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
5705 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5706 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5707 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
5708 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
5709 Inst = TmpInst; in processInstruction()
5722 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5723 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5724 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5725 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5726 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
5727 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5728 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5730 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5731 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
5732 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
5733 Inst = TmpInst; in processInstruction()
5746 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5747 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5748 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5749 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5750 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
5751 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5752 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5754 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5756 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5757 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
5758 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
5759 Inst = TmpInst; in processInstruction()
5772 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5773 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5774 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5775 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5776 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
5777 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5778 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5780 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5784 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5785 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
5786 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
5787 Inst = TmpInst; in processInstruction()
5798 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5799 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5800 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5801 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5803 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5804 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5805 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5806 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5807 Inst = TmpInst; in processInstruction()
5820 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5821 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5822 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5823 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5825 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5828 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5829 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5830 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5831 Inst = TmpInst; in processInstruction()
5844 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5845 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5846 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5847 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5849 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5854 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5855 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5856 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5857 Inst = TmpInst; in processInstruction()
5870 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5871 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5872 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5873 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5875 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5876 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5878 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5882 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5883 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5884 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5885 Inst = TmpInst; in processInstruction()
5896 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5897 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5898 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5899 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5900 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5901 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5902 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5903 Inst = TmpInst; in processInstruction()
5916 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5917 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5918 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5919 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5920 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5922 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5923 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5924 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5925 Inst = TmpInst; in processInstruction()
5938 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5939 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5940 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5941 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5942 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5944 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5946 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5947 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5948 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5949 Inst = TmpInst; in processInstruction()
5962 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5963 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5964 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5965 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5966 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5968 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
5972 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5973 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
5974 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
5975 Inst = TmpInst; in processInstruction()
5987 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5988 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
5989 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
5990 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
5991 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
5992 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
5993 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
5994 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
5995 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
5996 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
5997 Inst = TmpInst; in processInstruction()
6010 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6011 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6012 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6014 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6015 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6016 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6017 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
6018 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6019 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6021 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6022 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
6023 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
6024 Inst = TmpInst; in processInstruction()
6037 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6038 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6039 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6041 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6043 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6044 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6045 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6046 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
6047 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6048 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6050 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6052 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6053 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
6054 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
6055 Inst = TmpInst; in processInstruction()
6068 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6069 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6070 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6072 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6074 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6076 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6077 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6078 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6079 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
6080 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6087 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6088 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
6089 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
6090 Inst = TmpInst; in processInstruction()
6101 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6102 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6103 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6104 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6105 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6107 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6108 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6109 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6110 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6111 Inst = TmpInst; in processInstruction()
6124 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6125 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6126 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6128 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6129 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6130 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6132 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6135 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6136 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6137 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6138 Inst = TmpInst; in processInstruction()
6151 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6152 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6153 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6155 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6157 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6158 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6159 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6161 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6162 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6166 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6167 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6168 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6169 Inst = TmpInst; in processInstruction()
6182 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6183 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6184 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6186 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6190 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6191 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6192 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6194 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6197 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6199 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6201 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6202 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6203 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6204 Inst = TmpInst; in processInstruction()
6215 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6216 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6217 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6218 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6219 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6220 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6221 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6222 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6223 Inst = TmpInst; in processInstruction()
6236 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6237 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6240 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6241 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6242 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6243 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6245 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6246 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6247 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6248 Inst = TmpInst; in processInstruction()
6261 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6262 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6263 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6265 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6267 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6268 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6269 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6270 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6272 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6274 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6275 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6276 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6277 Inst = TmpInst; in processInstruction()
6290 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6291 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6292 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6294 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6296 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6298 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6299 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6300 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
6301 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6303 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6307 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6308 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6309 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6310 Inst = TmpInst; in processInstruction()
6323 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6324 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6325 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6327 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6329 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6330 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6331 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6332 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6333 Inst = TmpInst; in processInstruction()
6345 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6346 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6347 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6349 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6351 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6352 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6353 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6355 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6356 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6357 Inst = TmpInst; in processInstruction()
6369 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6370 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6371 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6373 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6375 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6376 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6377 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6378 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
6379 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6380 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6381 Inst = TmpInst; in processInstruction()
6394 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6395 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6398 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6400 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6401 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6402 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6403 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6404 Inst = TmpInst; in processInstruction()
6416 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6417 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6418 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6420 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6422 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6423 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6424 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6426 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6427 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6428 Inst = TmpInst; in processInstruction()
6440 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6441 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6442 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6446 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6447 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6448 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6449 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
6450 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6451 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6452 Inst = TmpInst; in processInstruction()
6465 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6466 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6473 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6474 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6475 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6476 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6477 Inst = TmpInst; in processInstruction()
6489 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6490 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6491 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6493 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6495 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6497 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6498 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6499 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6501 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6502 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6503 Inst = TmpInst; in processInstruction()
6515 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6516 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6519 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6521 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6523 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6524 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6525 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6526 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
6527 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6528 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6529 Inst = TmpInst; in processInstruction()
6542 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6543 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6546 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6548 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6550 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6551 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6552 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6553 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6554 Inst = TmpInst; in processInstruction()
6566 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6567 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6568 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6574 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6575 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6576 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6578 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6579 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6580 Inst = TmpInst; in processInstruction()
6592 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6593 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6594 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6596 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6598 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6600 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6601 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6602 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6603 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
6604 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6605 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6606 Inst = TmpInst; in processInstruction()
6619 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6620 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6621 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6622 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6623 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6625 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6627 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6628 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6629 Inst = TmpInst; in processInstruction()
6641 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6642 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6643 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6644 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6646 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6647 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6649 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6651 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6652 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6653 Inst = TmpInst; in processInstruction()
6665 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6666 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6667 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6668 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6669 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
6670 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6671 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6673 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6675 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6676 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6677 Inst = TmpInst; in processInstruction()
6690 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6691 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6692 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6693 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6700 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6701 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6702 Inst = TmpInst; in processInstruction()
6714 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6715 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6716 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6717 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6719 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6720 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6722 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6724 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6726 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6727 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6728 Inst = TmpInst; in processInstruction()
6740 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6741 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6742 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
6743 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
6744 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
6745 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6746 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6748 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6750 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + in processInstruction()
6752 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6753 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6754 Inst = TmpInst; in processInstruction()
6762 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
6763 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
6764 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
6768 switch (Inst.getOpcode()) { in processInstruction()
6777 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
6778 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6779 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6780 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
6781 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6782 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6783 Inst = TmpInst; in processInstruction()
6796 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
6797 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
6798 isARMLowRegister(Inst.getOperand(2).getReg()) && in processInstruction()
6799 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
6800 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) in processInstruction()
6804 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { in processInstruction()
6812 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
6815 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
6816 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6817 TmpInst.addOperand(Inst.getOperand(2)); // Rm in processInstruction()
6818 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6819 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6822 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
6823 Inst = TmpInst; in processInstruction()
6832 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
6833 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
6834 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) in processInstruction()
6838 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { in processInstruction()
6846 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); in processInstruction()
6849 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
6852 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
6853 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6856 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6857 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6860 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
6861 Inst = TmpInst; in processInstruction()
6870 switch(Inst.getOpcode()) { in processInstruction()
6880 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
6881 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6882 TmpInst.addOperand(Inst.getOperand(2)); // Rm in processInstruction()
6884 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6885 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6886 TmpInst.addOperand(Inst.getOperand(5)); // cc_out in processInstruction()
6887 Inst = TmpInst; in processInstruction()
6895 switch(Inst.getOpcode()) { in processInstruction()
6903 unsigned Amt = Inst.getOperand(2).getImm(); in processInstruction()
6911 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
6912 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6915 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
6916 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6917 TmpInst.addOperand(Inst.getOperand(5)); // cc_out in processInstruction()
6918 Inst = TmpInst; in processInstruction()
6925 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
6926 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6928 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
6929 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6930 TmpInst.addOperand(Inst.getOperand(4)); // cc_out in processInstruction()
6931 Inst = TmpInst; in processInstruction()
6937 if (Inst.getNumOperands() != 5) in processInstruction()
6941 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
6942 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
6943 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6945 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
6946 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6947 Inst = TmpInst; in processInstruction()
6953 if (Inst.getNumOperands() != 5) in processInstruction()
6957 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
6958 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
6959 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6961 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
6962 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6963 Inst = TmpInst; in processInstruction()
6970 Inst.getNumOperands() == 5) { in processInstruction()
6973 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
6974 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
6975 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
6978 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
6979 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6980 Inst = TmpInst; in processInstruction()
6988 Inst.getNumOperands() == 5) { in processInstruction()
6991 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
6992 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
6993 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 in processInstruction()
6995 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
6996 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6997 Inst = TmpInst; in processInstruction()
7004 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
7006 Inst.setOpcode(ARM::t2ADDri); in processInstruction()
7007 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out in processInstruction()
7013 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
7015 Inst.setOpcode(ARM::t2SUBri); in processInstruction()
7016 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out in processInstruction()
7023 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
7024 Inst.setOpcode(ARM::tADDi3); in processInstruction()
7033 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
7034 Inst.setOpcode(ARM::tSUBi3); in processInstruction()
7044 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || in processInstruction()
7045 !isARMLowRegister(Inst.getOperand(0).getReg()) || in processInstruction()
7046 (unsigned)Inst.getOperand(2).getImm() > 255 || in processInstruction()
7047 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || in processInstruction()
7048 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || in processInstruction()
7053 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? in processInstruction()
7055 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7056 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7057 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7058 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7059 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7060 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7061 Inst = TmpInst; in processInstruction()
7069 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || in processInstruction()
7070 Inst.getOperand(5).getReg() != 0 || in processInstruction()
7076 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7077 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7078 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7079 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7080 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7081 Inst = TmpInst; in processInstruction()
7087 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in processInstruction()
7088 Inst.setOpcode(ARM::t2ADDrr); in processInstruction()
7089 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out in processInstruction()
7096 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { in processInstruction()
7097 Inst.setOpcode(ARM::tBcc); in processInstruction()
7103 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ in processInstruction()
7104 Inst.setOpcode(ARM::t2Bcc); in processInstruction()
7110 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { in processInstruction()
7111 Inst.setOpcode(ARM::t2B); in processInstruction()
7117 if (Inst.getOperand(1).getImm() == ARMCC::AL) { in processInstruction()
7118 Inst.setOpcode(ARM::tB); in processInstruction()
7127 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction()
7132 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || in processInstruction()
7137 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); in processInstruction()
7141 Inst.insert(Inst.begin(), in processInstruction()
7142 MCOperand::CreateReg(Inst.getOperand(0).getReg())); in processInstruction()
7151 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction()
7153 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { in processInstruction()
7156 Inst.setOpcode(ARM::t2STMIA_UPD); in processInstruction()
7166 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) in processInstruction()
7169 Inst.setOpcode(ARM::t2LDMIA_UPD); in processInstruction()
7171 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); in processInstruction()
7172 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); in processInstruction()
7177 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) in processInstruction()
7180 Inst.setOpcode(ARM::t2STMDB_UPD); in processInstruction()
7182 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); in processInstruction()
7183 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); in processInstruction()
7189 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
7190 (unsigned)Inst.getOperand(1).getImm() <= 255 && in processInstruction()
7191 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && in processInstruction()
7192 Inst.getOperand(4).getReg() == ARM::CPSR) || in processInstruction()
7193 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && in processInstruction()
7199 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7200 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7201 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7202 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7203 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7204 Inst = TmpInst; in processInstruction()
7212 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
7213 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
7214 Inst.getOperand(2).getImm() == ARMCC::AL && in processInstruction()
7215 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
7220 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); in processInstruction()
7221 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7222 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7223 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7224 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7225 Inst = TmpInst; in processInstruction()
7236 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
7237 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
7238 Inst.getOperand(2).getImm() == 0 && in processInstruction()
7242 switch (Inst.getOpcode()) { in processInstruction()
7252 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7253 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7254 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7255 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7256 Inst = TmpInst; in processInstruction()
7262 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); in processInstruction()
7266 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { in processInstruction()
7270 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7271 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7272 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7273 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7274 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7275 Inst = TmpInst; in processInstruction()
7287 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); in processInstruction()
7289 switch (Inst.getOpcode()) { in processInstruction()
7300 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && in processInstruction()
7304 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7305 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7306 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7307 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7308 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7309 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
7310 Inst = TmpInst; in processInstruction()
7321 MCOperand &MO = Inst.getOperand(1); in processInstruction()
7325 if ((Inst.getOperand(0).getImm() & 1) == 0) { in processInstruction()
7334 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); in processInstruction()
7348 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
7349 isARMLowRegister(Inst.getOperand(2).getReg())) && in processInstruction()
7350 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
7351 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || in processInstruction()
7352 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && in processInstruction()
7356 switch (Inst.getOpcode()) { in processInstruction()
7367 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7368 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7369 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7370 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7371 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7372 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7373 Inst = TmpInst; in processInstruction()
7386 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
7387 isARMLowRegister(Inst.getOperand(2).getReg())) && in processInstruction()
7388 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || in processInstruction()
7389 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && in processInstruction()
7390 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || in processInstruction()
7391 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && in processInstruction()
7395 switch (Inst.getOpcode()) { in processInstruction()
7404 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7405 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7406 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { in processInstruction()
7407 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7408 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7410 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7411 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7413 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7414 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7415 Inst = TmpInst; in processInstruction()
7424 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { in checkTargetMatchPredicate() argument
7427 unsigned Opc = Inst.getOpcode(); in checkTargetMatchPredicate()
7432 assert(MCID.NumOperands == Inst.getNumOperands() && in checkTargetMatchPredicate()
7441 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
7445 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
7448 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
7455 isARMLowRegister(Inst.getOperand(1).getReg()) && in checkTargetMatchPredicate()
7456 isARMLowRegister(Inst.getOperand(2).getReg())) in checkTargetMatchPredicate()
7460 isARMLowRegister(Inst.getOperand(0).getReg()) && in checkTargetMatchPredicate()
7461 isARMLowRegister(Inst.getOperand(1).getReg())) in checkTargetMatchPredicate()
7472 MCInst Inst; in MatchAndEmitInstruction() local
7475 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, in MatchAndEmitInstruction()
7482 if (validateInstruction(Inst, Operands)) { in MatchAndEmitInstruction()
7493 while (processInstruction(Inst, Operands)) in MatchAndEmitInstruction()
7503 if (Inst.getOpcode() == ARM::ITasm) in MatchAndEmitInstruction()
7506 Inst.setLoc(IDLoc); in MatchAndEmitInstruction()
7507 Out.EmitInstruction(Inst); in MatchAndEmitInstruction()