6767       unsigned NewOpc;  in processInstruction()  local
6770       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;  in processInstruction()
6771       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;  in processInstruction()
6772       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;  in processInstruction()
6776       TmpInst.setOpcode(NewOpc);  in processInstruction()
7241       unsigned NewOpc;  in processInstruction()  local
7244       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;  in processInstruction()
7245       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;  in processInstruction()
7246       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;  in processInstruction()
7247       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;  in processInstruction()
7251       TmpInst.setOpcode(NewOpc);  in processInstruction()
7355       unsigned NewOpc;  in processInstruction()  local
7358         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;  in processInstruction()
7359         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;  in processInstruction()
7360         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;  in processInstruction()
7361         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;  in processInstruction()
7362         case ARM::t2RORrr: NewOpc = ARM::tROR; break;  in processInstruction()
7363         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;  in processInstruction()
7366       TmpInst.setOpcode(NewOpc);  in processInstruction()
7394       unsigned NewOpc;  in processInstruction()  local
7397         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;  in processInstruction()
7398         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;  in processInstruction()
7399         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;  in processInstruction()
7400         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;  in processInstruction()
7403       TmpInst.setOpcode(NewOpc);  in processInstruction()