Lines Matching refs:src3
238 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
240 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
492 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
495 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
513 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
514 mnemonic#"($src1+$src2<<#$src3) = $src4",
531 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
534 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
552 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
553 mnemonic#"($src1+$src2<<#$src3) = $src4.new",
585 u2ImmPred:$src3))),
587 u2ImmPred:$src3, IntRegs:$src4)>;
591 u2ImmPred:$src3))),
593 u2ImmPred:$src3, IntRegs:$src4)>;
596 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
598 u2ImmPred:$src3, IntRegs:$src4)>;
601 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
603 u2ImmPred:$src3, DoubleRegs:$src4)>;
609 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
610 mnemonic#"($src1<<#$src2+##$src3) = $src4",
613 u0AlwaysExtPred:$src3))]>,
619 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
620 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
645 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
646 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
650 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
651 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
680 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
682 ") ")#mnemonic#"($src2+#$src3) = #$src4",
700 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
701 mnemonic#"($src1+#$src2) = #$src3",
725 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
726 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
728 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
730 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
732 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
733 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
818 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
820 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
843 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
844 mnemonic#"($src1+#$src2) = $src3.new",
934 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
936 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1197 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1198 "$dst = add($src1, add($src2, #$src3))",
1201 s6_16ExtPred:$src3)))]>,
1208 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1209 "$dst = add($src1, sub(#$src2, $src3))",
1212 (i32 IntRegs:$src3))))]>,
1221 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1222 "$dst = add($src1, sub(#$src2, $src3))",
1225 (i32 IntRegs:$src3)))]>,
1260 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1261 "$dst ^= xor($src2, $src3)",
1264 (i64 DoubleRegs:$src3))))],
1274 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1275 "$dst = or($src1, and($src2, #$src3))",
1278 s10ExtPred:$src3)))],
1286 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1287 "$dst &= and($src2, $src3)",
1290 (i32 IntRegs:$src3))))],
1297 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1298 "$dst |= and($src2, $src3)",
1301 (i32 IntRegs:$src3))))],
1308 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1309 "$dst ^= and($src2, $src3)",
1312 (i32 IntRegs:$src3))))],
1320 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1321 "$dst &= and($src2, ~$src3)",
1324 (not (i32 IntRegs:$src3)))))],
1331 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1332 "$dst |= and($src2, ~$src3)",
1335 (not (i32 IntRegs:$src3)))))],
1342 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1343 "$dst ^= and($src2, ~$src3)",
1346 (not (i32 IntRegs:$src3)))))],
1354 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1355 "$dst &= or($src2, $src3)",
1358 (i32 IntRegs:$src3))))],
1365 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1366 "$dst |= or($src2, $src3)",
1369 (i32 IntRegs:$src3))))],
1376 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1377 "$dst ^= or($src2, $src3)",
1380 (i32 IntRegs:$src3))))],
1388 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1389 "$dst &= xor($src2, $src3)",
1392 (i32 IntRegs:$src3))))],
1399 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1400 "$dst |= xor($src2, $src3)",
1403 (i32 IntRegs:$src3))))],
1410 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1411 "$dst ^= xor($src2, $src3)",
1414 (i32 IntRegs:$src3))))],
1422 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1423 "$dst |= and($src2, #$src3)",
1426 s10ExtPred:$src3)))],
1434 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1435 "$dst |= or($src2, #$src3)",
1438 s10ExtPred:$src3)))],
1490 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1491 "$dst = add(#$src1, mpyi($src2, #$src3))",
1493 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1498 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1501 u6ImmPred:$src3))>;
1507 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1508 "$dst = add(#$src1, mpyi($src2, $src3))",
1510 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1515 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1518 IntRegs:$src3))>;
1523 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1524 "$dst = add($src1, mpyi(#$src2, $src3))",
1526 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1534 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1535 "$dst = add($src1, mpyi($src2, #$src3))",
1538 u6ExtPred:$src3)))]>,
1544 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1545 "$dst = add($src1, mpyi($src2, $src3))",
1548 (i32 IntRegs:$src3))))],
1596 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1597 "$dst = add(#$src1, asl($src2, #$src3))",
1599 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1608 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1609 "$dst = add(#$src1, lsr($src2, #$src3))",
1611 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1620 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1621 "$dst = sub(#$src1, asl($src2, #$src3))",
1623 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1632 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1633 "$dst = sub(#$src1, lsr($src2, #$src3))",
1635 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1646 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1647 "$dst = and(#$src1, asl($src2, #$src3))",
1649 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1658 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1659 "$dst = and(#$src1, lsr($src2, #$src3))",
1661 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1670 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1671 "$dst = or(#$src1, asl($src2, #$src3))",
1673 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1682 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1683 "$dst = or(#$src1, lsr($src2, #$src3))",
1685 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1704 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1705 "$dst ^= asl($src2, $src3)",
1708 (i32 IntRegs:$src3))))],
1714 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1715 "$dst ^= asr($src2, $src3)",
1718 (i32 IntRegs:$src3))))],
1724 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1725 "$dst ^= lsl($src2, $src3)",
1728 (i32 IntRegs:$src3))))],
1734 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1735 "$dst ^= lsr($src2, $src3)",
1738 (i32 IntRegs:$src3))))],
3185 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3186 "memw($src1+#$src2) = ##$src3",
3187 [(store (HexagonCONST32 tglobaladdr:$src3),
3283 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3284 "memh($src1+#$src2) = ##$src3",
3285 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),