Lines Matching refs:VA
337 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
338 if (VA.isRegLoc()) { in LowerCCCArguments()
340 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
352 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
358 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
360 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
361 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
363 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
365 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
366 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
372 assert(VA.isMemLoc()); in LowerCCCArguments()
379 VA.getLocMemOffset(), true); in LowerCCCArguments()
383 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
386 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
390 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); in LowerCCCArguments()
395 InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
433 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
434 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
436 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
442 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
490 CCValAssign &VA = ArgLocs[i]; in LowerCCCCallTo() local
495 switch (VA.getLocInfo()) { in LowerCCCCallTo()
499 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
502 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
505 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
511 if (VA.isRegLoc()) { in LowerCCCCallTo()
512 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
514 assert(VA.isMemLoc()); in LowerCCCCallTo()
521 DAG.getIntPtrConstant(VA.getLocMemOffset())); in LowerCCCCallTo()