Lines Matching refs:ry
139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
192 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
201 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
206 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
216 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
223 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
224 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
231 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
232 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
274 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
275 !strconcat(asmstr, "\t$rx, $ry"), []>;
281 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
282 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
291 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
301 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
302 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
306 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
307 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
313 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
314 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
317 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
318 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
328 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
329 !strconcat(asmstr, "\t$rz, $ry"),
351 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
352 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
532 // Format: ADDU rz, rx, ry MIPS16e
540 // Format: AND rx, ry MIPS16e
635 // Format: CMP rx, ry MIPS16e
663 // Format: DIV rx, ry MIPS16e
672 // Format: DIVU rx, ry MIPS16e
723 // Format: LB ry, offset(rx) MIPS16e
732 // Format: LBU ry, offset(rx) MIPS16e
742 // Format: LH ry, offset(rx) MIPS16e
751 // Format: LHU ry, offset(rx) MIPS16e
775 // Format: LW ry, offset(rx) MIPS16e
799 // Format: MOVE ry, r32 MIPS16e
841 // Format: MULT rx, ry MIPS16e
852 // Format: MULTU rx, ry MIPS16e
863 // Format: NEG rx, ry MIPS16e
870 // Format: NOT rx, ry MIPS16e
877 // Format: OR rx, ry MIPS16e
946 // Format: SB ry, offset(rx) MIPS16e
1068 // Format: SH ry, offset(rx) MIPS16e
1076 // Format: SLL rx, ry, sa MIPS16e
1083 // Format: SLLV ry, rx MIPS16e
1136 // Format: SLT rx, ry MIPS16e
1146 // Format: SLTU rx, ry MIPS16e
1162 // Format: SRAV ry, rx MIPS16e
1171 // Format: SRA rx, ry, sa MIPS16e
1180 // Format: SRLV ry, rx MIPS16e
1189 // Format: SRL rx, ry, sa MIPS16e
1197 // Format: SUBU rz, rx, ry MIPS16e
1204 // Format: SW ry, offset(rx) MIPS16e
1221 // Format: XOR rx, ry MIPS16e
1320 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1321 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1364 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1365 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1383 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1384 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1391 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1392 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1406 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1407 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1419 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1420 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1427 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1428 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1455 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1456 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1463 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1464 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1472 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1473 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1488 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1489 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1495 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1496 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;