Lines Matching refs:SP
55 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_f64()
91 Reg = SP::I0 + Offset/8; in CC_Sparc64_Full()
94 Reg = SP::D0 + Offset/8; in CC_Sparc64_Full()
97 Reg = SP::F1 + Offset/4; in CC_Sparc64_Full()
126 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, in CC_Sparc64_Half()
133 unsigned Reg = SP::I0 + Offset/8; in CC_Sparc64_Half()
156 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); in toCallerWindow()
157 if (Reg >= SP::I0 && Reg <= SP::I7) in toCallerWindow()
158 return Reg - SP::I0 + SP::O0; in toCallerWindow()
217 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); in LowerReturn_32()
219 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); in LowerReturn_32()
367 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
384 &SP::IntRegsRegClass); in LowerFormalArguments_32()
393 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
477 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
487 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in LowerFormalArguments_32()
505 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
627 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64()
747 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
764 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
797 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
807 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
838 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
960 unsigned Offset = 8 * (VA.getLocReg() - SP::D0); in fixupVariableFloatArgs()
965 unsigned IReg = SP::I0 + Offset/8; in fixupVariableFloatArgs()
1070 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); in LowerCall_64()
1244 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1245 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1246 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1248 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1372 setStackPointerRegisterToSaveRestore(SP::O6); in SparcTargetLowering()
1638 DAG.getRegister(SP::I6, TLI.getPointerTy()), in LowerVASTART()
1673 unsigned SPReg = SP::O6; in LowerDYNAMIC_STACKALLOC()
1674 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); in LowerDYNAMIC_STACKALLOC() local
1675 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
1676 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain in LowerDYNAMIC_STACKALLOC()
1700 unsigned FrameReg = SP::I6; in LowerFRAMEADDR()
1737 unsigned RetReg = MF.addLiveIn(SP::I7, in LowerRETURNADDR()
1746 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); in LowerRETURNADDR()
1774 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
1776 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
1783 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
1785 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
1825 case SP::SELECT_CC_Int_ICC: in EmitInstrWithCustomInserter()
1826 case SP::SELECT_CC_FP_ICC: in EmitInstrWithCustomInserter()
1827 case SP::SELECT_CC_DFP_ICC: in EmitInstrWithCustomInserter()
1828 BROpcode = SP::BCOND; in EmitInstrWithCustomInserter()
1830 case SP::SELECT_CC_Int_FCC: in EmitInstrWithCustomInserter()
1831 case SP::SELECT_CC_FP_FCC: in EmitInstrWithCustomInserter()
1832 case SP::SELECT_CC_DFP_FCC: in EmitInstrWithCustomInserter()
1833 BROpcode = SP::FBCOND; in EmitInstrWithCustomInserter()
1883 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) in EmitInstrWithCustomInserter()
1915 return std::make_pair(0U, &SP::IntRegsRegClass); in getRegForInlineAsmConstraint()