Lines Matching refs:VA
198 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
199 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
201 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), in LowerReturn_32()
206 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
261 CCValAssign &VA = RVLocs[i]; in LowerReturn_64() local
262 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
266 switch (VA.getLocInfo()) { in LowerReturn_64()
268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
274 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
281 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
287 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
295 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
299 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
351 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32() local
364 if (VA.isRegLoc()) { in LowerFormalArguments_32()
365 if (VA.needsCustom()) { in LowerFormalArguments_32()
366 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments_32()
368 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
396 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
398 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
400 DAG.getValueType(VA.getLocVT())); in LowerFormalArguments_32()
401 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
407 assert(VA.isMemLoc()); in LowerFormalArguments_32()
409 unsigned Offset = VA.getLocMemOffset()+StackOffset; in LowerFormalArguments_32()
411 if (VA.needsCustom()) { in LowerFormalArguments_32()
412 assert(VA.getValVT() == MVT::f64); in LowerFormalArguments_32()
419 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, in LowerFormalArguments_32()
454 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
455 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, in LowerFormalArguments_32()
461 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); in LowerFormalArguments_32()
466 VA.getValVT(), false, false,0); in LowerFormalArguments_32()
467 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); in LowerFormalArguments_32()
550 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_64() local
551 if (VA.isRegLoc()) { in LowerFormalArguments_64()
556 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
557 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
558 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); in LowerFormalArguments_64()
561 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
562 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
567 switch (VA.getLocInfo()) { in LowerFormalArguments_64()
569 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
570 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
573 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
574 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
581 if (VA.isExtInLoc()) in LowerFormalArguments_64()
582 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
589 assert(VA.isMemLoc()); in LowerFormalArguments_64()
592 unsigned Offset = VA.getLocMemOffset() + ArgArea; in LowerFormalArguments_64()
593 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments_64()
597 if (VA.isExtInLoc()) in LowerFormalArguments_64()
600 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, in LowerFormalArguments_64()
717 CCValAssign &VA = ArgLocs[i]; in LowerCall_32() local
727 switch (VA.getLocInfo()) { in LowerCall_32()
731 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
734 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
737 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
740 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
745 assert(VA.needsCustom()); in LowerCall_32()
757 if (VA.needsCustom()) { in LowerCall_32()
758 assert(VA.getLocVT() == MVT::f64); in LowerCall_32()
760 if (VA.isMemLoc()) { in LowerCall_32()
761 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
788 if (VA.isRegLoc()) { in LowerCall_32()
789 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); in LowerCall_32()
805 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
825 if (VA.isRegLoc()) { in LowerCall_32()
826 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
827 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
831 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
835 assert(VA.isMemLoc()); in LowerCall_32()
839 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); in LowerCall_32()
947 const CCValAssign &VA = ArgLocs[i]; in fixupVariableFloatArgs() local
950 if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64) in fixupVariableFloatArgs()
953 if (Outs[VA.getValNo()].IsFixed) in fixupVariableFloatArgs()
960 unsigned Offset = 8 * (VA.getLocReg() - SP::D0); in fixupVariableFloatArgs()
967 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
971 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
972 Offset, VA.getLocVT(), VA.getLocInfo()); in fixupVariableFloatArgs()
1022 const CCValAssign &VA = ArgLocs[i]; in LowerCall_64() local
1026 switch (VA.getLocInfo()) { in LowerCall_64()
1032 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1035 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1038 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1041 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1045 if (VA.isRegLoc()) { in LowerCall_64()
1048 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
1055 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerCall_64()
1063 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); in LowerCall_64()
1067 assert(VA.isMemLoc()); in LowerCall_64()
1073 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + in LowerCall_64()
1141 CCValAssign &VA = RVLocs[i]; in LowerCall_64() local
1142 unsigned Reg = toCallerWindow(VA.getLocReg()); in LowerCall_64()
1160 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerCall_64()
1161 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1166 switch (VA.getLocInfo()) { in LowerCall_64()
1168 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1169 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1172 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1173 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1180 if (VA.isExtInLoc()) in LowerCall_64()
1181 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()