Lines Matching refs:SETCC
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom); in resetOperationActions()
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom); in resetOperationActions()
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom); in resetOperationActions()
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom); in resetOperationActions()
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom); in resetOperationActions()
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom); in resetOperationActions()
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom); in resetOperationActions()
846 setOperationAction(ISD::SETCC, VT, Expand); in resetOperationActions()
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in resetOperationActions()
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in resetOperationActions()
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); in resetOperationActions()
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); in resetOperationActions()
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); in resetOperationActions()
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in resetOperationActions()
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); in resetOperationActions()
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); in resetOperationActions()
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom); in resetOperationActions()
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom); in resetOperationActions()
1520 setTargetDAGCombine(ISD::SETCC); in resetOperationActions()
5656 if (In.getOpcode() == ISD::SETCC) { in LowerBUILD_VECTORvXi1()
5668 } else if (In.getOpcode() == X86ISD::SETCC) { in LowerBUILD_VECTORvXi1()
9336 UI->getOpcode() != ISD::SETCC && in EmitTest()
9376 User->getOpcode() != ISD::SETCC && in EmitTest()
9586 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerToBT()
9643 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC && in Lower256IntVSETCC()
9876 if (Op0.getOpcode() == X86ISD::SETCC) { in LowerSETCC()
9883 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC()
9895 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC()
9952 if (Cond.getOpcode() == ISD::SETCC && in LowerSELECT()
9970 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
9980 if (Cond.getOpcode() == X86ISD::SETCC && in LowerSELECT()
10037 if (CondOpcode == X86ISD::SETCC || in LowerSELECT()
10206 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && in isAndOrOfSetCCs()
10208 Op.getOperand(1).getOpcode() == X86ISD::SETCC && in isAndOrOfSetCCs()
10219 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && in isXor1OfSetCC()
10234 if (Cond.getOpcode() == ISD::SETCC) { in LowerBRCOND()
10274 if (CondOpcode == X86ISD::SETCC || in LowerBRCOND()
10396 } else if (Cond.getOpcode() == ISD::SETCC && in LowerBRCOND()
10427 } else if (Cond.getOpcode() == ISD::SETCC && in LowerBRCOND()
10847 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_WO_CHAIN()
11144 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); in LowerINTRINSIC_WO_CHAIN()
11300 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_WO_CHAIN()
11429 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_W_CHAIN()
12484 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in LowerXALUO()
12497 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), in LowerXALUO()
12835 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
13131 case X86ISD::SETCC: return "X86ISD::SETCC"; in getTargetNodeName()
15429 case X86ISD::SETCC: in computeMaskedBitsForTargetNode()
15934 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && in PerformSELECTCombine()
16086 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. in PerformSELECTCombine()
16182 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && in PerformSELECTCombine()
16200 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC && in PerformSELECTCombine()
16255 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) in PerformSELECTCombine()
16261 Cond.getOpcode() == ISD::SETCC) { in PerformSELECTCombine()
16413 case X86ISD::SETCC: in checkBoolTestSetCCCombine()
16518 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in PerformCMOVCombine()
16535 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in PerformCMOVCombine()
16573 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in PerformCMOVCombine()
18158 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags); in PerformSETCCCombine()
18256 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) in OptimizeConditionalInDecrement()
18386 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); in PerformDAGCombine()
18387 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()