Lines Matching refs:v8i32
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); in resetOperationActions()
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); in resetOperationActions()
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); in resetOperationActions()
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); in resetOperationActions()
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); in resetOperationActions()
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal); in resetOperationActions()
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal); in resetOperationActions()
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal); in resetOperationActions()
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom); in resetOperationActions()
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom); in resetOperationActions()
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom); in resetOperationActions()
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom); in resetOperationActions()
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom); in resetOperationActions()
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom); in resetOperationActions()
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom); in resetOperationActions()
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal); in resetOperationActions()
1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal); in resetOperationActions()
1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom); in resetOperationActions()
1619 return MVT::v8i32; in getOptimalMemOpType()
1725 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: in findRepresentativeClass()
3833 if (VT != MVT::v8i32 && VT != MVT::v8f32) in Compact8x32ShuffleNode()
4652 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, in getZeroVector()
4681 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, in getOnesVector()
4685 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); in getOnesVector()
5723 if (VT == MVT::v4i32 || VT == MVT::v8i32) in LowerBUILD_VECTOR()
5733 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256())) in LowerBUILD_VECTOR()
5833 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); in LowerBUILD_VECTOR()
6576 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; in RewriteAsNarrowerShuffle()
6577 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; in RewriteAsNarrowerShuffle()
7400 if (HasInt256 && VT == MVT::v8i32) in LowerVECTOR_SHUFFLE()
7416 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { in LowerVECTOR_SHUFFLE()
7421 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, in LowerVECTOR_SHUFFLE()
8771 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) && in LowerAVXExtend()
8833 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi); in LowerZERO_EXTEND()
8846 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In); in LowerTRUNCATE()
8847 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32), in LowerTRUNCATE()
8873 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) { in LowerTRUNCATE()
8960 MVT::v8i32, Op.getOperand(0))); in LowerFP_TO_SINT()
10160 (VT != MVT::v8i32 || InVT != MVT::v8i16)) in LowerSIGN_EXTEND()
11936 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; in LowerMUL()
12013 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { in LowerScalarImmediateShift()
12175 VT == MVT::v8i32 || VT == MVT::v16i16))) { in LowerScalarVariableShift()
12241 case MVT::v8i32: in LowerScalarVariableShift()
12250 case MVT::v8i32: in LowerScalarVariableShift()
12261 case MVT::v8i32: in LowerScalarVariableShift()
12323 VT == MVT::v4i64 || VT == MVT::v8i32)) in LowerShift()
12327 VT == MVT::v4i64 || VT == MVT::v8i32)) in LowerShift()
12329 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32)) in LowerShift()
12519 case MVT::v8i32: in LowerSIGN_EXTEND_INREG()
15859 case MVT::v8i32: in matchIntegerMINMAX()
16752 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) in performShiftToAllZeros()
18195 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; in PerformSINT_TO_FPCombine()
18292 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && in PerformAddCombine()
18325 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && in PerformSubCombine()
19007 case MVT::v8i32: in getRegForInlineAsmConstraint()