Lines Matching refs:RC

119                     RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
122   def r     : FMA3<opc, MRMSrcReg, (outs RC:$dst),
123                    (ins RC:$src1, RC:$src2, RC:$src3),
126                    [(set RC:$dst,
127                      (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
129   def m     : FMA3<opc, MRMSrcMem, (outs RC:$dst),
130                    (ins RC:$src1, RC:$src2, x86memop:$src3),
133                    [(set RC:$dst,
134                      (OpVT (OpNode RC:$src2, RC:$src1,
140                         RegisterClass RC> {
159                        SDNode OpNode, RegisterClass RC, ValueType OpVT,
164                        x86memop, RC, OpVT, mem_frag>;
166                        x86memop, RC, OpVT, mem_frag>;
170                      x86memop, RC, OpVT, mem_frag, OpNode>,
172                          memop, mem_cpat, Int, RC>;
200 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
204   def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
205            (ins RC:$src1, RC:$src2, RC:$src3),
208            [(set RC:$dst,
209              (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, MemOp4;
210   def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst),
211            (ins RC:$src1, RC:$src2, x86memop:$src3),
214            [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
216   def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
217            (ins RC:$src1, x86memop:$src2, RC:$src3),
220            [(set RC:$dst,
221              (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>;
224   def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
225                (ins RC:$src1, RC:$src2, RC:$src3),