Lines Matching refs:MRMSrcReg
164 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
185 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
231 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
467 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
773 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1080 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1083 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1086 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1089 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1331 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1338 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1347 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1353 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1421 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1433 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1444 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1580 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1594 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1748 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1765 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1776 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1783 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1792 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1799 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1811 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1838 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1859 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1874 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1891 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1910 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1926 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1941 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1960 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1967 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1977 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1989 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2043 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2083 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2097 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2105 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2118 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2134 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2145 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2156 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2173 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2188 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2201 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2259 def rr : SIi8<0xC2, MRMSrcReg,
2272 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2308 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2346 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2407 def rri : PIi8<0xC2, MRMSrcReg,
2420 def rri_alt : PIi8<0xC2, MRMSrcReg,
2505 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2589 def rr : PI<opc, MRMSrcReg,
2689 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2693 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2721 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2724 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2728 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2731 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2767 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3080 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3101 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3112 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3126 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3147 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3159 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3175 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3185 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3197 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3212 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3222 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3235 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3249 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3270 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3279 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3293 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3303 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3315 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3562 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3565 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3568 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3571 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3633 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3636 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3707 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3748 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3779 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4079 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4097 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4115 def ri : Ii8<0x70, MRMSrcReg,
4159 def rr : PDI<opc, MRMSrcReg,
4180 def Yrr : PDI<opc, MRMSrcReg,
4260 def rri : Ii8<0xC4, MRMSrcReg,
4283 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4289 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4299 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4316 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4320 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4324 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4327 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4331 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4345 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4351 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4358 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4363 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4377 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4388 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4393 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4398 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4408 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4413 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4421 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4431 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4539 def VMOVZDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4544 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4552 def MOVZDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4557 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4718 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4724 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4766 def VMOVQs64rr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4784 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4786 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4796 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4857 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4870 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4950 def rr : I<0xD0, MRMSrcReg,
4996 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5012 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5069 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5087 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5212 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5235 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5256 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5386 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5406 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5493 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5506 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5666 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5679 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5744 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5758 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6169 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6194 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6220 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6250 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6289 def PSr : SS4AIi8<opcps, MRMSrcReg,
6308 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6333 def SSr : SS4AIi8<opcss, MRMSrcReg,
6343 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6367 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6377 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6541 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6550 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6561 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6574 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6601 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6610 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6619 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6634 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6656 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6676 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6694 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6805 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6893 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6992 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7084 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7134 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7169 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7204 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7240 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7273 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7285 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7297 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7309 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7322 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7336 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7377 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7389 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7403 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7416 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7434 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7448 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7494 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7500 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7505 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7538 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7577 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7765 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7775 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7820 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7882 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7920 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7957 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7964 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8101 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8124 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8147 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8182 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8325 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8338 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),