Lines Matching refs:VEX_LIG
487 VEX_4V, VEX_LIG;
492 VEX, VEX_LIG, Sched<[WriteStore]>;
511 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
1458 XS, VEX, VEX_LIG;
1462 XS, VEX, VEX_W, VEX_LIG;
1466 XD, VEX, VEX_LIG;
1470 XD, VEX, VEX_W, VEX_LIG;
1494 XS, VEX_4V, VEX_LIG;
1496 XS, VEX_4V, VEX_W, VEX_LIG;
1498 XD, VEX_4V, VEX_LIG;
1500 XD, VEX_4V, VEX_W, VEX_LIG;
1611 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1614 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1684 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1687 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1751 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1758 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1815 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1822 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
2287 XS, VEX_4V, VEX_LIG;
2292 XD, VEX_4V, VEX_LIG;
2361 "ucomiss">, TB, VEX, VEX_LIG;
2363 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2366 "comiss">, TB, VEX, VEX_LIG;
2368 "comisd">, TB, OpSize, VEX, VEX_LIG;
2991 VEX_4V, VEX_LIG;
2994 VEX_4V, VEX_LIG;
2999 VEX_4V, VEX_LIG;
3002 VEX_4V, VEX_LIG;
3005 VEX_4V, VEX_LIG;
3008 VEX_4V, VEX_LIG;
3031 VEX_4V, VEX_LIG;
3033 VEX_4V, VEX_LIG;
3084 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3090 []>, VEX_4V, VEX_LIG,
3096 []>, VEX_4V, VEX_LIG,
3130 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3136 []>, VEX_4V, VEX_LIG,
3142 []>, VEX_4V, VEX_LIG,
3253 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3259 []>, VEX_4V, VEX_LIG,
3265 []>, VEX_4V, VEX_LIG,
6414 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;