Lines Matching refs:MRMDestReg

700 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), 
706 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), 
712 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), 
717 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
722 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), 
728 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), 
737 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
744 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
751 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
758 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
765 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
772 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,