Lines Matching refs:i16
3 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
6 %tmp1 = load <8 x i16>* %A
7 …@llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
11 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
15 …%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -1…
16 ret <4 x i16> %tmp2
27 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
30 %tmp1 = load <8 x i16>* %A
31 …@llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
35 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
39 …%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -1…
40 ret <4 x i16> %tmp2
51 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
54 %tmp1 = load <8 x i16>* %A
55 …llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
59 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
63 …%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -…
64 ret <4 x i16> %tmp2
75 declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
76 declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
79 declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
80 declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
83 declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
84 declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
87 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
90 %tmp1 = load <8 x i16>* %A
91 …llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
95 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
99 …%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -…
100 ret <4 x i16> %tmp2
111 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
114 %tmp1 = load <8 x i16>* %A
115 …llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
119 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
123 …%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -…
124 ret <4 x i16> %tmp2
135 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
138 %tmp1 = load <8 x i16>* %A
139 …lvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
143 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
147 …%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 …
148 ret <4 x i16> %tmp2
159 declare <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
160 declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
163 declare <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
164 declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
167 declare <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
168 declare <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone