Lines Matching refs:pci_conf
238 uint8_t *pci_conf = d->config; in piix3_reset() local
240 pci_conf[0x04] = 0x07; // master, memory and I/O in piix3_reset()
241 pci_conf[0x05] = 0x00; in piix3_reset()
242 pci_conf[0x06] = 0x00; in piix3_reset()
243 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium in piix3_reset()
244 pci_conf[0x4c] = 0x4d; in piix3_reset()
245 pci_conf[0x4e] = 0x03; in piix3_reset()
246 pci_conf[0x4f] = 0x00; in piix3_reset()
247 pci_conf[0x60] = 0x80; in piix3_reset()
248 pci_conf[0x61] = 0x80; in piix3_reset()
249 pci_conf[0x62] = 0x80; in piix3_reset()
250 pci_conf[0x63] = 0x80; in piix3_reset()
251 pci_conf[0x69] = 0x02; in piix3_reset()
252 pci_conf[0x70] = 0x80; in piix3_reset()
253 pci_conf[0x76] = 0x0c; in piix3_reset()
254 pci_conf[0x77] = 0x0c; in piix3_reset()
255 pci_conf[0x78] = 0x02; in piix3_reset()
256 pci_conf[0x79] = 0x00; in piix3_reset()
257 pci_conf[0x80] = 0x00; in piix3_reset()
258 pci_conf[0x82] = 0x00; in piix3_reset()
259 pci_conf[0xa0] = 0x08; in piix3_reset()
260 pci_conf[0xa2] = 0x00; in piix3_reset()
261 pci_conf[0xa3] = 0x00; in piix3_reset()
262 pci_conf[0xa4] = 0x00; in piix3_reset()
263 pci_conf[0xa5] = 0x00; in piix3_reset()
264 pci_conf[0xa6] = 0x00; in piix3_reset()
265 pci_conf[0xa7] = 0x00; in piix3_reset()
266 pci_conf[0xa8] = 0x0f; in piix3_reset()
267 pci_conf[0xaa] = 0x00; in piix3_reset()
268 pci_conf[0xab] = 0x00; in piix3_reset()
269 pci_conf[0xac] = 0x00; in piix3_reset()
270 pci_conf[0xae] = 0x00; in piix3_reset()
278 uint8_t *pci_conf = d->config; in piix4_reset() local
280 pci_conf[0x04] = 0x07; // master, memory and I/O in piix4_reset()
281 pci_conf[0x05] = 0x00; in piix4_reset()
282 pci_conf[0x06] = 0x00; in piix4_reset()
283 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium in piix4_reset()
284 pci_conf[0x4c] = 0x4d; in piix4_reset()
285 pci_conf[0x4e] = 0x03; in piix4_reset()
286 pci_conf[0x4f] = 0x00; in piix4_reset()
287 pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 in piix4_reset()
288 pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 in piix4_reset()
289 pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 in piix4_reset()
290 pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 in piix4_reset()
291 pci_conf[0x69] = 0x02; in piix4_reset()
292 pci_conf[0x70] = 0x80; in piix4_reset()
293 pci_conf[0x76] = 0x0c; in piix4_reset()
294 pci_conf[0x77] = 0x0c; in piix4_reset()
295 pci_conf[0x78] = 0x02; in piix4_reset()
296 pci_conf[0x79] = 0x00; in piix4_reset()
297 pci_conf[0x80] = 0x00; in piix4_reset()
298 pci_conf[0x82] = 0x00; in piix4_reset()
299 pci_conf[0xa0] = 0x08; in piix4_reset()
300 pci_conf[0xa2] = 0x00; in piix4_reset()
301 pci_conf[0xa3] = 0x00; in piix4_reset()
302 pci_conf[0xa4] = 0x00; in piix4_reset()
303 pci_conf[0xa5] = 0x00; in piix4_reset()
304 pci_conf[0xa6] = 0x00; in piix4_reset()
305 pci_conf[0xa7] = 0x00; in piix4_reset()
306 pci_conf[0xa8] = 0x0f; in piix4_reset()
307 pci_conf[0xaa] = 0x00; in piix4_reset()
308 pci_conf[0xab] = 0x00; in piix4_reset()
309 pci_conf[0xac] = 0x00; in piix4_reset()
310 pci_conf[0xae] = 0x00; in piix4_reset()
332 uint8_t *pci_conf; in piix3_init() local
339 pci_conf = d->config; in piix3_init()
341 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); in piix3_init()
342 …pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bri… in piix3_init()
343 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); in piix3_init()
344 pci_conf[PCI_HEADER_TYPE] = in piix3_init()
355 uint8_t *pci_conf; in piix4_init() local
362 pci_conf = d->config; in piix4_init()
364 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); in piix4_init()
365 …pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-I… in piix4_init()
366 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); in piix4_init()
367 pci_conf[PCI_HEADER_TYPE] = in piix4_init()