290           && e->Iex.Const.con->Ico.U64 == 0ULL;  in isZeroU64()
297           && e->Iex.Const.con->Ico.U32 == 0;  in isZeroU32()
364       if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) {  in iselIntExpr_single_instruction()
367                    AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64)),  in iselIntExpr_single_instruction()
371          return AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, dst);  in iselIntExpr_single_instruction()
495           && guard->Iex.Const.con->Ico.U1 == True) {  in doHelperCall()
570           && guard->Iex.Const.con->Ico.U1 == True) {  in doHelperCall()
965             nshift = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;  in iselIntExpr_R_wrk()
1690          addInstr(env, AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, r));  in iselIntExpr_R_wrk()
1812           && imm8->Iex.Const.con->Ico.U8 < 4  in iselIntExpr_AMode_wrk()
1816           && fitsIn32Bits(simm32->Iex.Const.con->Ico.U64)) {  in iselIntExpr_AMode_wrk()
1817          UInt shift = imm8->Iex.Const.con->Ico.U8;  in iselIntExpr_AMode_wrk()
1818          UInt offset = toUInt(simm32->Iex.Const.con->Ico.U64);  in iselIntExpr_AMode_wrk()
1833       UInt shift = e->Iex.Binop.arg2->Iex.Binop.arg2->Iex.Const.con->Ico.U8;  in iselIntExpr_AMode_wrk()
1846        && fitsIn32Bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) {  in iselIntExpr_AMode_wrk()
1849                 toUInt(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64),   in iselIntExpr_AMode_wrk()
1898            if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) {  in iselIntExpr_RMI_wrk()
1899               return AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64));  in iselIntExpr_RMI_wrk()
1903             return AMD64RMI_Imm(e->Iex.Const.con->Ico.U32); break;  in iselIntExpr_RMI_wrk()
1905             return AMD64RMI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16); break;  in iselIntExpr_RMI_wrk()
1907             return AMD64RMI_Imm(0xFF & e->Iex.Const.con->Ico.U8); break;  in iselIntExpr_RMI_wrk()
1967            if (fitsIn32Bits(e->Iex.Const.con->Ico.U64)) {  in iselIntExpr_RI_wrk()
1968               return AMD64RI_Imm(toUInt(e->Iex.Const.con->Ico.U64));  in iselIntExpr_RI_wrk()
1972             return AMD64RI_Imm(e->Iex.Const.con->Ico.U32);  in iselIntExpr_RI_wrk()
1974             return AMD64RI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16);  in iselIntExpr_RI_wrk()
1976             return AMD64RI_Imm(0xFF & e->Iex.Const.con->Ico.U8);  in iselIntExpr_RI_wrk()
2068       vassert(e->Iex.Const.con->Ico.U1 == True   in iselCondCode_wrk()
2069               || e->Iex.Const.con->Ico.U1 == False);  in iselCondCode_wrk()
2073       return e->Iex.Const.con->Ico.U1 ? Acc_Z : Acc_NZ;  in iselCondCode_wrk()
2211       addInstr(env, AMD64Instr_Imm64(con->Iex.Const.con->Ico.U64, tmp));  in iselCondCode_wrk()
2524          u.f64 = e->Iex.Const.con->Ico.F64;  in iselDblExpr_wrk()
2527          u.u64 = e->Iex.Const.con->Ico.F64i;  in iselDblExpr_wrk()
2860       switch (e->Iex.Const.con->Ico.V128) {  in iselVecExpr_wrk()
2871                                 (e->Iex.Const.con->Ico.V128 >> 8) & 0xFF  in iselVecExpr_wrk()
2874                                 (e->Iex.Const.con->Ico.V128 >> 0) & 0xFF  in iselVecExpr_wrk()
3447       switch (e->Iex.Const.con->Ico.V256) {  in iselDVecExpr_wrk()
4043                = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga;  in iselStmt()
4045             addInstr(env, AMD64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64,  in iselStmt()
4117                = ((Addr64)cdst->Ico.U64) > env->max_ga;  in iselNext()
4119             addInstr(env, AMD64Instr_XDirect(cdst->Ico.U64,   in iselNext()