1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "HexagonInstrInfo.h"
15 #include "Hexagon.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
29 #define GET_INSTRINFO_CTOR
30 #define GET_INSTRMAP_INFO
31 #include "HexagonGenInstrInfo.inc"
32 #include "HexagonGenDFAPacketizer.inc"
33
34 using namespace llvm;
35
36 ///
37 /// Constants for Hexagon instructions.
38 ///
39 const int Hexagon_MEMW_OFFSET_MAX = 4095;
40 const int Hexagon_MEMW_OFFSET_MIN = -4096;
41 const int Hexagon_MEMD_OFFSET_MAX = 8191;
42 const int Hexagon_MEMD_OFFSET_MIN = -8192;
43 const int Hexagon_MEMH_OFFSET_MAX = 2047;
44 const int Hexagon_MEMH_OFFSET_MIN = -2048;
45 const int Hexagon_MEMB_OFFSET_MAX = 1023;
46 const int Hexagon_MEMB_OFFSET_MIN = -1024;
47 const int Hexagon_ADDI_OFFSET_MAX = 32767;
48 const int Hexagon_ADDI_OFFSET_MIN = -32768;
49 const int Hexagon_MEMD_AUTOINC_MAX = 56;
50 const int Hexagon_MEMD_AUTOINC_MIN = -64;
51 const int Hexagon_MEMW_AUTOINC_MAX = 28;
52 const int Hexagon_MEMW_AUTOINC_MIN = -32;
53 const int Hexagon_MEMH_AUTOINC_MAX = 14;
54 const int Hexagon_MEMH_AUTOINC_MIN = -16;
55 const int Hexagon_MEMB_AUTOINC_MAX = 7;
56 const int Hexagon_MEMB_AUTOINC_MIN = -8;
57
58
HexagonInstrInfo(HexagonSubtarget & ST)59 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
60 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
61 RI(ST), Subtarget(ST) {
62 }
63
64
65 /// isLoadFromStackSlot - If the specified machine instruction is a direct
66 /// load from a stack slot, return the virtual or physical register number of
67 /// the destination along with the FrameIndex of the loaded stack slot. If
68 /// not, return 0. This predicate must return 0 if the instruction has
69 /// any side effects other than loading from the stack slot.
isLoadFromStackSlot(const MachineInstr * MI,int & FrameIndex) const70 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
71 int &FrameIndex) const {
72
73
74 switch (MI->getOpcode()) {
75 default: break;
76 case Hexagon::LDriw:
77 case Hexagon::LDrid:
78 case Hexagon::LDrih:
79 case Hexagon::LDrib:
80 case Hexagon::LDriub:
81 if (MI->getOperand(2).isFI() &&
82 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
83 FrameIndex = MI->getOperand(2).getIndex();
84 return MI->getOperand(0).getReg();
85 }
86 break;
87 }
88 return 0;
89 }
90
91
92 /// isStoreToStackSlot - If the specified machine instruction is a direct
93 /// store to a stack slot, return the virtual or physical register number of
94 /// the source reg along with the FrameIndex of the loaded stack slot. If
95 /// not, return 0. This predicate must return 0 if the instruction has
96 /// any side effects other than storing to the stack slot.
isStoreToStackSlot(const MachineInstr * MI,int & FrameIndex) const97 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const {
99 switch (MI->getOpcode()) {
100 default: break;
101 case Hexagon::STriw:
102 case Hexagon::STrid:
103 case Hexagon::STrih:
104 case Hexagon::STrib:
105 if (MI->getOperand(2).isFI() &&
106 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
107 FrameIndex = MI->getOperand(0).getIndex();
108 return MI->getOperand(2).getReg();
109 }
110 break;
111 }
112 return 0;
113 }
114
115
116 unsigned
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,const SmallVectorImpl<MachineOperand> & Cond,DebugLoc DL) const117 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
118 MachineBasicBlock *FBB,
119 const SmallVectorImpl<MachineOperand> &Cond,
120 DebugLoc DL) const{
121
122 int BOpc = Hexagon::JMP;
123 int BccOpc = Hexagon::JMP_t;
124
125 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
126
127 int regPos = 0;
128 // Check if ReverseBranchCondition has asked to reverse this branch
129 // If we want to reverse the branch an odd number of times, we want
130 // JMP_f.
131 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
132 BccOpc = Hexagon::JMP_f;
133 regPos = 1;
134 }
135
136 if (FBB == 0) {
137 if (Cond.empty()) {
138 // Due to a bug in TailMerging/CFG Optimization, we need to add a
139 // special case handling of a predicated jump followed by an
140 // unconditional jump. If not, Tail Merging and CFG Optimization go
141 // into an infinite loop.
142 MachineBasicBlock *NewTBB, *NewFBB;
143 SmallVector<MachineOperand, 4> Cond;
144 MachineInstr *Term = MBB.getFirstTerminator();
145 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
146 false)) {
147 MachineBasicBlock *NextBB =
148 llvm::next(MachineFunction::iterator(&MBB));
149 if (NewTBB == NextBB) {
150 ReverseBranchCondition(Cond);
151 RemoveBranch(MBB);
152 return InsertBranch(MBB, TBB, 0, Cond, DL);
153 }
154 }
155 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
156 } else {
157 BuildMI(&MBB, DL,
158 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
159 }
160 return 1;
161 }
162
163 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
164 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
165
166 return 2;
167 }
168
169
AnalyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const170 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
171 MachineBasicBlock *&TBB,
172 MachineBasicBlock *&FBB,
173 SmallVectorImpl<MachineOperand> &Cond,
174 bool AllowModify) const {
175 TBB = NULL;
176 FBB = NULL;
177
178 // If the block has no terminators, it just falls into the block after it.
179 MachineBasicBlock::instr_iterator I = MBB.instr_end();
180 if (I == MBB.instr_begin())
181 return false;
182
183 // A basic block may looks like this:
184 //
185 // [ insn
186 // EH_LABEL
187 // insn
188 // insn
189 // insn
190 // EH_LABEL
191 // insn ]
192 //
193 // It has two succs but does not have a terminator
194 // Don't know how to handle it.
195 do {
196 --I;
197 if (I->isEHLabel())
198 return true;
199 } while (I != MBB.instr_begin());
200
201 I = MBB.instr_end();
202 --I;
203
204 while (I->isDebugValue()) {
205 if (I == MBB.instr_begin())
206 return false;
207 --I;
208 }
209
210 // Delete the JMP if it's equivalent to a fall-through.
211 if (AllowModify && I->getOpcode() == Hexagon::JMP &&
212 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
213 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
214 I->eraseFromParent();
215 I = MBB.instr_end();
216 if (I == MBB.instr_begin())
217 return false;
218 --I;
219 }
220 if (!isUnpredicatedTerminator(I))
221 return false;
222
223 // Get the last instruction in the block.
224 MachineInstr *LastInst = I;
225 MachineInstr *SecondLastInst = NULL;
226 // Find one more terminator if present.
227 do {
228 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
229 if (!SecondLastInst)
230 SecondLastInst = I;
231 else
232 // This is a third branch.
233 return true;
234 }
235 if (I == MBB.instr_begin())
236 break;
237 --I;
238 } while(I);
239
240 int LastOpcode = LastInst->getOpcode();
241
242 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
243 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
244
245 // If there is only one terminator instruction, process it.
246 if (LastInst && !SecondLastInst) {
247 if (LastOpcode == Hexagon::JMP) {
248 TBB = LastInst->getOperand(0).getMBB();
249 return false;
250 }
251 if (LastOpcode == Hexagon::ENDLOOP0) {
252 TBB = LastInst->getOperand(0).getMBB();
253 Cond.push_back(LastInst->getOperand(0));
254 return false;
255 }
256 if (LastOpcodeHasJMP_c) {
257 TBB = LastInst->getOperand(1).getMBB();
258 if (LastOpcodeHasNot) {
259 Cond.push_back(MachineOperand::CreateImm(0));
260 }
261 Cond.push_back(LastInst->getOperand(0));
262 return false;
263 }
264 // Otherwise, don't know what this is.
265 return true;
266 }
267
268 int SecLastOpcode = SecondLastInst->getOpcode();
269
270 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
271 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
272 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
273 TBB = SecondLastInst->getOperand(1).getMBB();
274 if (SecLastOpcodeHasNot)
275 Cond.push_back(MachineOperand::CreateImm(0));
276 Cond.push_back(SecondLastInst->getOperand(0));
277 FBB = LastInst->getOperand(0).getMBB();
278 return false;
279 }
280
281 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
282 // executed, so remove it.
283 if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
284 TBB = SecondLastInst->getOperand(0).getMBB();
285 I = LastInst;
286 if (AllowModify)
287 I->eraseFromParent();
288 return false;
289 }
290
291 // If the block ends with an ENDLOOP, and JMP, handle it.
292 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
293 LastOpcode == Hexagon::JMP) {
294 TBB = SecondLastInst->getOperand(0).getMBB();
295 Cond.push_back(SecondLastInst->getOperand(0));
296 FBB = LastInst->getOperand(0).getMBB();
297 return false;
298 }
299
300 // Otherwise, can't handle this.
301 return true;
302 }
303
304
RemoveBranch(MachineBasicBlock & MBB) const305 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
306 int BOpc = Hexagon::JMP;
307 int BccOpc = Hexagon::JMP_t;
308 int BccOpcNot = Hexagon::JMP_f;
309
310 MachineBasicBlock::iterator I = MBB.end();
311 if (I == MBB.begin()) return 0;
312 --I;
313 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
314 I->getOpcode() != BccOpcNot)
315 return 0;
316
317 // Remove the branch.
318 I->eraseFromParent();
319
320 I = MBB.end();
321
322 if (I == MBB.begin()) return 1;
323 --I;
324 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
325 return 1;
326
327 // Remove the branch.
328 I->eraseFromParent();
329 return 2;
330 }
331
332
333 /// \brief For a comparison instruction, return the source registers in
334 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
335 /// compares against in CmpValue. Return true if the comparison instruction
336 /// can be analyzed.
analyzeCompare(const MachineInstr * MI,unsigned & SrcReg,unsigned & SrcReg2,int & Mask,int & Value) const337 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
338 unsigned &SrcReg, unsigned &SrcReg2,
339 int &Mask, int &Value) const {
340 unsigned Opc = MI->getOpcode();
341
342 // Set mask and the first source register.
343 switch (Opc) {
344 case Hexagon::CMPEHexagon4rr:
345 case Hexagon::CMPEQri:
346 case Hexagon::CMPEQrr:
347 case Hexagon::CMPGT64rr:
348 case Hexagon::CMPGTU64rr:
349 case Hexagon::CMPGTUri:
350 case Hexagon::CMPGTUrr:
351 case Hexagon::CMPGTri:
352 case Hexagon::CMPGTrr:
353 SrcReg = MI->getOperand(1).getReg();
354 Mask = ~0;
355 break;
356 case Hexagon::CMPbEQri_V4:
357 case Hexagon::CMPbEQrr_sbsb_V4:
358 case Hexagon::CMPbEQrr_ubub_V4:
359 case Hexagon::CMPbGTUri_V4:
360 case Hexagon::CMPbGTUrr_V4:
361 case Hexagon::CMPbGTrr_V4:
362 SrcReg = MI->getOperand(1).getReg();
363 Mask = 0xFF;
364 break;
365 case Hexagon::CMPhEQri_V4:
366 case Hexagon::CMPhEQrr_shl_V4:
367 case Hexagon::CMPhEQrr_xor_V4:
368 case Hexagon::CMPhGTUri_V4:
369 case Hexagon::CMPhGTUrr_V4:
370 case Hexagon::CMPhGTrr_shl_V4:
371 SrcReg = MI->getOperand(1).getReg();
372 Mask = 0xFFFF;
373 break;
374 }
375
376 // Set the value/second source register.
377 switch (Opc) {
378 case Hexagon::CMPEHexagon4rr:
379 case Hexagon::CMPEQrr:
380 case Hexagon::CMPGT64rr:
381 case Hexagon::CMPGTU64rr:
382 case Hexagon::CMPGTUrr:
383 case Hexagon::CMPGTrr:
384 case Hexagon::CMPbEQrr_sbsb_V4:
385 case Hexagon::CMPbEQrr_ubub_V4:
386 case Hexagon::CMPbGTUrr_V4:
387 case Hexagon::CMPbGTrr_V4:
388 case Hexagon::CMPhEQrr_shl_V4:
389 case Hexagon::CMPhEQrr_xor_V4:
390 case Hexagon::CMPhGTUrr_V4:
391 case Hexagon::CMPhGTrr_shl_V4:
392 SrcReg2 = MI->getOperand(2).getReg();
393 return true;
394
395 case Hexagon::CMPEQri:
396 case Hexagon::CMPGTUri:
397 case Hexagon::CMPGTri:
398 case Hexagon::CMPbEQri_V4:
399 case Hexagon::CMPbGTUri_V4:
400 case Hexagon::CMPhEQri_V4:
401 case Hexagon::CMPhGTUri_V4:
402 SrcReg2 = 0;
403 Value = MI->getOperand(2).getImm();
404 return true;
405 }
406
407 return false;
408 }
409
410
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const411 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I, DebugLoc DL,
413 unsigned DestReg, unsigned SrcReg,
414 bool KillSrc) const {
415 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
416 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
417 return;
418 }
419 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
420 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
421 return;
422 }
423 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
424 // Map Pd = Ps to Pd = or(Ps, Ps).
425 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
426 DestReg).addReg(SrcReg).addReg(SrcReg);
427 return;
428 }
429 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
430 Hexagon::IntRegsRegClass.contains(SrcReg)) {
431 // We can have an overlap between single and double reg: r1:0 = r0.
432 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
433 // r1:0 = r0
434 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
435 Hexagon::subreg_hireg))).addImm(0);
436 } else {
437 // r1:0 = r1 or no overlap.
438 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
439 Hexagon::subreg_loreg))).addReg(SrcReg);
440 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
441 Hexagon::subreg_hireg))).addImm(0);
442 }
443 return;
444 }
445 if (Hexagon::CRRegsRegClass.contains(DestReg) &&
446 Hexagon::IntRegsRegClass.contains(SrcReg)) {
447 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
448 return;
449 }
450 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
451 Hexagon::IntRegsRegClass.contains(DestReg)) {
452 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
453 addReg(SrcReg, getKillRegState(KillSrc));
454 return;
455 }
456 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
457 Hexagon::PredRegsRegClass.contains(DestReg)) {
458 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
459 addReg(SrcReg, getKillRegState(KillSrc));
460 return;
461 }
462
463 llvm_unreachable("Unimplemented");
464 }
465
466
467 void HexagonInstrInfo::
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const468 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
469 unsigned SrcReg, bool isKill, int FI,
470 const TargetRegisterClass *RC,
471 const TargetRegisterInfo *TRI) const {
472
473 DebugLoc DL = MBB.findDebugLoc(I);
474 MachineFunction &MF = *MBB.getParent();
475 MachineFrameInfo &MFI = *MF.getFrameInfo();
476 unsigned Align = MFI.getObjectAlignment(FI);
477
478 MachineMemOperand *MMO =
479 MF.getMachineMemOperand(
480 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
481 MachineMemOperand::MOStore,
482 MFI.getObjectSize(FI),
483 Align);
484
485 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
486 BuildMI(MBB, I, DL, get(Hexagon::STriw))
487 .addFrameIndex(FI).addImm(0)
488 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
489 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
490 BuildMI(MBB, I, DL, get(Hexagon::STrid))
491 .addFrameIndex(FI).addImm(0)
492 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
493 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
494 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
495 .addFrameIndex(FI).addImm(0)
496 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
497 } else {
498 llvm_unreachable("Unimplemented");
499 }
500 }
501
502
storeRegToAddr(MachineFunction & MF,unsigned SrcReg,bool isKill,SmallVectorImpl<MachineOperand> & Addr,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs) const503 void HexagonInstrInfo::storeRegToAddr(
504 MachineFunction &MF, unsigned SrcReg,
505 bool isKill,
506 SmallVectorImpl<MachineOperand> &Addr,
507 const TargetRegisterClass *RC,
508 SmallVectorImpl<MachineInstr*> &NewMIs) const
509 {
510 llvm_unreachable("Unimplemented");
511 }
512
513
514 void HexagonInstrInfo::
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const515 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
516 unsigned DestReg, int FI,
517 const TargetRegisterClass *RC,
518 const TargetRegisterInfo *TRI) const {
519 DebugLoc DL = MBB.findDebugLoc(I);
520 MachineFunction &MF = *MBB.getParent();
521 MachineFrameInfo &MFI = *MF.getFrameInfo();
522 unsigned Align = MFI.getObjectAlignment(FI);
523
524 MachineMemOperand *MMO =
525 MF.getMachineMemOperand(
526 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
527 MachineMemOperand::MOLoad,
528 MFI.getObjectSize(FI),
529 Align);
530 if (RC == &Hexagon::IntRegsRegClass) {
531 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
532 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
533 } else if (RC == &Hexagon::DoubleRegsRegClass) {
534 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
535 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
536 } else if (RC == &Hexagon::PredRegsRegClass) {
537 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
538 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
539 } else {
540 llvm_unreachable("Can't store this register to stack slot");
541 }
542 }
543
544
loadRegFromAddr(MachineFunction & MF,unsigned DestReg,SmallVectorImpl<MachineOperand> & Addr,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs) const545 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
546 SmallVectorImpl<MachineOperand> &Addr,
547 const TargetRegisterClass *RC,
548 SmallVectorImpl<MachineInstr*> &NewMIs) const {
549 llvm_unreachable("Unimplemented");
550 }
551
552
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr * MI,const SmallVectorImpl<unsigned> & Ops,int FI) const553 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
554 MachineInstr* MI,
555 const SmallVectorImpl<unsigned> &Ops,
556 int FI) const {
557 // Hexagon_TODO: Implement.
558 return(0);
559 }
560
createVR(MachineFunction * MF,MVT VT) const561 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
562
563 MachineRegisterInfo &RegInfo = MF->getRegInfo();
564 const TargetRegisterClass *TRC;
565 if (VT == MVT::i1) {
566 TRC = &Hexagon::PredRegsRegClass;
567 } else if (VT == MVT::i32 || VT == MVT::f32) {
568 TRC = &Hexagon::IntRegsRegClass;
569 } else if (VT == MVT::i64 || VT == MVT::f64) {
570 TRC = &Hexagon::DoubleRegsRegClass;
571 } else {
572 llvm_unreachable("Cannot handle this register class");
573 }
574
575 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
576 return NewReg;
577 }
578
isExtendable(const MachineInstr * MI) const579 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
580 // Constant extenders are allowed only for V4 and above.
581 if (!Subtarget.hasV4TOps())
582 return false;
583
584 const MCInstrDesc &MID = MI->getDesc();
585 const uint64_t F = MID.TSFlags;
586 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
587 return true;
588
589 // TODO: This is largely obsolete now. Will need to be removed
590 // in consecutive patches.
591 switch(MI->getOpcode()) {
592 // TFR_FI Remains a special case.
593 case Hexagon::TFR_FI:
594 return true;
595 default:
596 return false;
597 }
598 return false;
599 }
600
601 // This returns true in two cases:
602 // - The OP code itself indicates that this is an extended instruction.
603 // - One of MOs has been marked with HMOTF_ConstExtended flag.
isExtended(const MachineInstr * MI) const604 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
605 // First check if this is permanently extended op code.
606 const uint64_t F = MI->getDesc().TSFlags;
607 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
608 return true;
609 // Use MO operand flags to determine if one of MI's operands
610 // has HMOTF_ConstExtended flag set.
611 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
612 E = MI->operands_end(); I != E; ++I) {
613 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
614 return true;
615 }
616 return false;
617 }
618
isBranch(const MachineInstr * MI) const619 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
620 return MI->getDesc().isBranch();
621 }
622
isNewValueInst(const MachineInstr * MI) const623 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
624 if (isNewValueJump(MI))
625 return true;
626
627 if (isNewValueStore(MI))
628 return true;
629
630 return false;
631 }
632
isSaveCalleeSavedRegsCall(const MachineInstr * MI) const633 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
634 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
635 }
636
isPredicable(MachineInstr * MI) const637 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
638 bool isPred = MI->getDesc().isPredicable();
639
640 if (!isPred)
641 return false;
642
643 const int Opc = MI->getOpcode();
644
645 switch(Opc) {
646 case Hexagon::TFRI:
647 return isInt<12>(MI->getOperand(1).getImm());
648
649 case Hexagon::STrid:
650 case Hexagon::STrid_indexed:
651 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
652
653 case Hexagon::STriw:
654 case Hexagon::STriw_indexed:
655 case Hexagon::STriw_nv_V4:
656 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
657
658 case Hexagon::STrih:
659 case Hexagon::STrih_indexed:
660 case Hexagon::STrih_nv_V4:
661 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
662
663 case Hexagon::STrib:
664 case Hexagon::STrib_indexed:
665 case Hexagon::STrib_nv_V4:
666 return isUInt<6>(MI->getOperand(1).getImm());
667
668 case Hexagon::LDrid:
669 case Hexagon::LDrid_indexed:
670 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
671
672 case Hexagon::LDriw:
673 case Hexagon::LDriw_indexed:
674 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
675
676 case Hexagon::LDrih:
677 case Hexagon::LDriuh:
678 case Hexagon::LDrih_indexed:
679 case Hexagon::LDriuh_indexed:
680 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
681
682 case Hexagon::LDrib:
683 case Hexagon::LDriub:
684 case Hexagon::LDrib_indexed:
685 case Hexagon::LDriub_indexed:
686 return isUInt<6>(MI->getOperand(2).getImm());
687
688 case Hexagon::POST_LDrid:
689 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
690
691 case Hexagon::POST_LDriw:
692 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
693
694 case Hexagon::POST_LDrih:
695 case Hexagon::POST_LDriuh:
696 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
697
698 case Hexagon::POST_LDrib:
699 case Hexagon::POST_LDriub:
700 return isInt<4>(MI->getOperand(3).getImm());
701
702 case Hexagon::STrib_imm_V4:
703 case Hexagon::STrih_imm_V4:
704 case Hexagon::STriw_imm_V4:
705 return (isUInt<6>(MI->getOperand(1).getImm()) &&
706 isInt<6>(MI->getOperand(2).getImm()));
707
708 case Hexagon::ADD_ri:
709 return isInt<8>(MI->getOperand(2).getImm());
710
711 case Hexagon::ASLH:
712 case Hexagon::ASRH:
713 case Hexagon::SXTB:
714 case Hexagon::SXTH:
715 case Hexagon::ZXTB:
716 case Hexagon::ZXTH:
717 return Subtarget.hasV4TOps();
718 }
719
720 return true;
721 }
722
723 // This function performs the following inversiones:
724 //
725 // cPt ---> cNotPt
726 // cNotPt ---> cPt
727 //
getInvertedPredicatedOpcode(const int Opc) const728 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
729 int InvPredOpcode;
730 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
731 : Hexagon::getTruePredOpcode(Opc);
732 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
733 return InvPredOpcode;
734
735 switch(Opc) {
736 default: llvm_unreachable("Unexpected predicated instruction");
737 case Hexagon::COMBINE_rr_cPt:
738 return Hexagon::COMBINE_rr_cNotPt;
739 case Hexagon::COMBINE_rr_cNotPt:
740 return Hexagon::COMBINE_rr_cPt;
741
742 // Dealloc_return.
743 case Hexagon::DEALLOC_RET_cPt_V4:
744 return Hexagon::DEALLOC_RET_cNotPt_V4;
745 case Hexagon::DEALLOC_RET_cNotPt_V4:
746 return Hexagon::DEALLOC_RET_cPt_V4;
747 }
748 }
749
750 // New Value Store instructions.
isNewValueStore(const MachineInstr * MI) const751 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
752 const uint64_t F = MI->getDesc().TSFlags;
753
754 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
755 }
756
isNewValueStore(unsigned Opcode) const757 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
758 const uint64_t F = get(Opcode).TSFlags;
759
760 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
761 }
762
763 int HexagonInstrInfo::
getMatchingCondBranchOpcode(int Opc,bool invertPredicate) const764 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
765 enum Hexagon::PredSense inPredSense;
766 inPredSense = invertPredicate ? Hexagon::PredSense_false :
767 Hexagon::PredSense_true;
768 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
769 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
770 return CondOpcode;
771
772 // This switch case will be removed once all the instructions have been
773 // modified to use relation maps.
774 switch(Opc) {
775 case Hexagon::TFRI_f:
776 return !invertPredicate ? Hexagon::TFRI_cPt_f :
777 Hexagon::TFRI_cNotPt_f;
778 case Hexagon::COMBINE_rr:
779 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
780 Hexagon::COMBINE_rr_cNotPt;
781
782 // Word.
783 case Hexagon::STriw_f:
784 return !invertPredicate ? Hexagon::STriw_cPt :
785 Hexagon::STriw_cNotPt;
786 case Hexagon::STriw_indexed_f:
787 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
788 Hexagon::STriw_indexed_cNotPt;
789
790 // DEALLOC_RETURN.
791 case Hexagon::DEALLOC_RET_V4:
792 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
793 Hexagon::DEALLOC_RET_cNotPt_V4;
794 }
795 llvm_unreachable("Unexpected predicable instruction");
796 }
797
798
799 bool HexagonInstrInfo::
PredicateInstruction(MachineInstr * MI,const SmallVectorImpl<MachineOperand> & Cond) const800 PredicateInstruction(MachineInstr *MI,
801 const SmallVectorImpl<MachineOperand> &Cond) const {
802 int Opc = MI->getOpcode();
803 assert (isPredicable(MI) && "Expected predicable instruction");
804 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
805 (Cond[0].getImm() == 0));
806
807 // This will change MI's opcode to its predicate version.
808 // However, its operand list is still the old one, i.e. the
809 // non-predicate one.
810 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
811
812 int oper = -1;
813 unsigned int GAIdx = 0;
814
815 // Indicates whether the current MI has a GlobalAddress operand
816 bool hasGAOpnd = false;
817 std::vector<MachineOperand> tmpOpnds;
818
819 // Indicates whether we need to shift operands to right.
820 bool needShift = true;
821
822 // The predicate is ALWAYS the FIRST input operand !!!
823 if (MI->getNumOperands() == 0) {
824 // The non-predicate version of MI does not take any operands,
825 // i.e. no outs and no ins. In this condition, the predicate
826 // operand will be directly placed at Operands[0]. No operand
827 // shift is needed.
828 // Example: BARRIER
829 needShift = false;
830 oper = -1;
831 }
832 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
833 && MI->getOperand(MI->getNumOperands()-1).isDef()
834 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
835 // The non-predicate version of MI does not have any input operands.
836 // In this condition, we extend the length of Operands[] by one and
837 // copy the original last operand to the newly allocated slot.
838 // At this moment, it is just a place holder. Later, we will put
839 // predicate operand directly into it. No operand shift is needed.
840 // Example: r0=BARRIER (this is a faked insn used here for illustration)
841 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
842 needShift = false;
843 oper = MI->getNumOperands() - 2;
844 }
845 else {
846 // We need to right shift all input operands by one. Duplicate the
847 // last operand into the newly allocated slot.
848 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
849 }
850
851 if (needShift)
852 {
853 // Operands[ MI->getNumOperands() - 2 ] has been copied into
854 // Operands[ MI->getNumOperands() - 1 ], so we start from
855 // Operands[ MI->getNumOperands() - 3 ].
856 // oper is a signed int.
857 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
858 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
859 {
860 MachineOperand &MO = MI->getOperand(oper);
861
862 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
863 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
864 // /\~
865 // /||\~
866 // ||
867 // Predicate Operand here
868 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
869 break;
870 }
871 if (MO.isReg()) {
872 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
873 MO.isImplicit(), MO.isKill(),
874 MO.isDead(), MO.isUndef(),
875 MO.isDebug());
876 }
877 else if (MO.isImm()) {
878 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
879 }
880 else if (MO.isGlobal()) {
881 // MI can not have more than one GlobalAddress operand.
882 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
883
884 // There is no member function called "ChangeToGlobalAddress" in the
885 // MachineOperand class (not like "ChangeToRegister" and
886 // "ChangeToImmediate"). So we have to remove them from Operands[] list
887 // first, and then add them back after we have inserted the predicate
888 // operand. tmpOpnds[] is to remember these operands before we remove
889 // them.
890 tmpOpnds.push_back(MO);
891
892 // Operands[oper] is a GlobalAddress operand;
893 // Operands[oper+1] has been copied into Operands[oper+2];
894 hasGAOpnd = true;
895 GAIdx = oper;
896 continue;
897 }
898 else {
899 assert(false && "Unexpected operand type");
900 }
901 }
902 }
903
904 int regPos = invertJump ? 1 : 0;
905 MachineOperand PredMO = Cond[regPos];
906
907 // [oper] now points to the last explicit Def. Predicate operand must be
908 // located at [oper+1]. See diagram above.
909 // This assumes that the predicate is always the first operand,
910 // i.e. Operands[0+numResults], in the set of inputs
911 // It is better to have an assert here to check this. But I don't know how
912 // to write this assert because findFirstPredOperandIdx() would return -1
913 if (oper < -1) oper = -1;
914
915 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
916 PredMO.isImplicit(), false,
917 PredMO.isDead(), PredMO.isUndef(),
918 PredMO.isDebug());
919
920 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
921 RegInfo.clearKillFlags(PredMO.getReg());
922
923 if (hasGAOpnd)
924 {
925 unsigned int i;
926
927 // Operands[GAIdx] is the original GlobalAddress operand, which is
928 // already copied into tmpOpnds[0].
929 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
930 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
931 // so we start from [GAIdx+2]
932 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
933 tmpOpnds.push_back(MI->getOperand(i));
934
935 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
936 // It is very important that we always remove from the end of Operands[]
937 // MI->getNumOperands() is at least 2 if program goes to here.
938 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
939 MI->RemoveOperand(i);
940
941 for (i = 0; i < tmpOpnds.size(); ++i)
942 MI->addOperand(tmpOpnds[i]);
943 }
944
945 return true;
946 }
947
948
949 bool
950 HexagonInstrInfo::
isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,const BranchProbability & Probability) const951 isProfitableToIfCvt(MachineBasicBlock &MBB,
952 unsigned NumCycles,
953 unsigned ExtraPredCycles,
954 const BranchProbability &Probability) const {
955 return true;
956 }
957
958
959 bool
960 HexagonInstrInfo::
isProfitableToIfCvt(MachineBasicBlock & TMBB,unsigned NumTCycles,unsigned ExtraTCycles,MachineBasicBlock & FMBB,unsigned NumFCycles,unsigned ExtraFCycles,const BranchProbability & Probability) const961 isProfitableToIfCvt(MachineBasicBlock &TMBB,
962 unsigned NumTCycles,
963 unsigned ExtraTCycles,
964 MachineBasicBlock &FMBB,
965 unsigned NumFCycles,
966 unsigned ExtraFCycles,
967 const BranchProbability &Probability) const {
968 return true;
969 }
970
971 // Returns true if an instruction is predicated irrespective of the predicate
972 // sense. For example, all of the following will return true.
973 // if (p0) R1 = add(R2, R3)
974 // if (!p0) R1 = add(R2, R3)
975 // if (p0.new) R1 = add(R2, R3)
976 // if (!p0.new) R1 = add(R2, R3)
isPredicated(const MachineInstr * MI) const977 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
978 const uint64_t F = MI->getDesc().TSFlags;
979
980 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
981 }
982
isPredicated(unsigned Opcode) const983 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
984 const uint64_t F = get(Opcode).TSFlags;
985
986 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
987 }
988
isPredicatedTrue(const MachineInstr * MI) const989 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
990 const uint64_t F = MI->getDesc().TSFlags;
991
992 assert(isPredicated(MI));
993 return (!((F >> HexagonII::PredicatedFalsePos) &
994 HexagonII::PredicatedFalseMask));
995 }
996
isPredicatedTrue(unsigned Opcode) const997 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
998 const uint64_t F = get(Opcode).TSFlags;
999
1000 // Make sure that the instruction is predicated.
1001 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1002 return (!((F >> HexagonII::PredicatedFalsePos) &
1003 HexagonII::PredicatedFalseMask));
1004 }
1005
isPredicatedNew(const MachineInstr * MI) const1006 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1007 const uint64_t F = MI->getDesc().TSFlags;
1008
1009 assert(isPredicated(MI));
1010 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1011 }
1012
isPredicatedNew(unsigned Opcode) const1013 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1014 const uint64_t F = get(Opcode).TSFlags;
1015
1016 assert(isPredicated(Opcode));
1017 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1018 }
1019
1020 // Returns true, if a ST insn can be promoted to a new-value store.
mayBeNewStore(const MachineInstr * MI) const1021 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1022 const HexagonRegisterInfo& QRI = getRegisterInfo();
1023 const uint64_t F = MI->getDesc().TSFlags;
1024
1025 return ((F >> HexagonII::mayNVStorePos) &
1026 HexagonII::mayNVStoreMask &
1027 QRI.Subtarget.hasV4TOps());
1028 }
1029
1030 bool
DefinesPredicate(MachineInstr * MI,std::vector<MachineOperand> & Pred) const1031 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1032 std::vector<MachineOperand> &Pred) const {
1033 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1034 MachineOperand MO = MI->getOperand(oper);
1035 if (MO.isReg() && MO.isDef()) {
1036 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1037 if (RC == &Hexagon::PredRegsRegClass) {
1038 Pred.push_back(MO);
1039 return true;
1040 }
1041 }
1042 }
1043 return false;
1044 }
1045
1046
1047 bool
1048 HexagonInstrInfo::
SubsumesPredicate(const SmallVectorImpl<MachineOperand> & Pred1,const SmallVectorImpl<MachineOperand> & Pred2) const1049 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1050 const SmallVectorImpl<MachineOperand> &Pred2) const {
1051 // TODO: Fix this
1052 return false;
1053 }
1054
1055
1056 //
1057 // We indicate that we want to reverse the branch by
1058 // inserting a 0 at the beginning of the Cond vector.
1059 //
1060 bool HexagonInstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const1061 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1062 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1063 Cond.erase(Cond.begin());
1064 } else {
1065 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1066 }
1067 return false;
1068 }
1069
1070
1071 bool HexagonInstrInfo::
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumInstrs,const BranchProbability & Probability) const1072 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1073 const BranchProbability &Probability) const {
1074 return (NumInstrs <= 4);
1075 }
1076
isDeallocRet(const MachineInstr * MI) const1077 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1078 switch (MI->getOpcode()) {
1079 default: return false;
1080 case Hexagon::DEALLOC_RET_V4 :
1081 case Hexagon::DEALLOC_RET_cPt_V4 :
1082 case Hexagon::DEALLOC_RET_cNotPt_V4 :
1083 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1084 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1085 case Hexagon::DEALLOC_RET_cdnPt_V4 :
1086 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1087 return true;
1088 }
1089 }
1090
1091
1092 bool HexagonInstrInfo::
isValidOffset(const int Opcode,const int Offset) const1093 isValidOffset(const int Opcode, const int Offset) const {
1094 // This function is to check whether the "Offset" is in the correct range of
1095 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1096 // inserted to calculate the final address. Due to this reason, the function
1097 // assumes that the "Offset" has correct alignment.
1098 // We used to assert if the offset was not properly aligned, however,
1099 // there are cases where a misaligned pointer recast can cause this
1100 // problem, and we need to allow for it. The front end warns of such
1101 // misaligns with respect to load size.
1102
1103 switch(Opcode) {
1104
1105 case Hexagon::LDriw:
1106 case Hexagon::LDriw_indexed:
1107 case Hexagon::LDriw_f:
1108 case Hexagon::STriw_indexed:
1109 case Hexagon::STriw:
1110 case Hexagon::STriw_f:
1111 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1112 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1113
1114 case Hexagon::LDrid:
1115 case Hexagon::LDrid_indexed:
1116 case Hexagon::LDrid_f:
1117 case Hexagon::STrid:
1118 case Hexagon::STrid_indexed:
1119 case Hexagon::STrid_f:
1120 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1121 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1122
1123 case Hexagon::LDrih:
1124 case Hexagon::LDriuh:
1125 case Hexagon::STrih:
1126 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1127 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1128
1129 case Hexagon::LDrib:
1130 case Hexagon::STrib:
1131 case Hexagon::LDriub:
1132 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1133 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1134
1135 case Hexagon::ADD_ri:
1136 case Hexagon::TFR_FI:
1137 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1138 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1139
1140 case Hexagon::MemOPw_ADDi_V4 :
1141 case Hexagon::MemOPw_SUBi_V4 :
1142 case Hexagon::MemOPw_ADDr_V4 :
1143 case Hexagon::MemOPw_SUBr_V4 :
1144 case Hexagon::MemOPw_ANDr_V4 :
1145 case Hexagon::MemOPw_ORr_V4 :
1146 return (0 <= Offset && Offset <= 255);
1147
1148 case Hexagon::MemOPh_ADDi_V4 :
1149 case Hexagon::MemOPh_SUBi_V4 :
1150 case Hexagon::MemOPh_ADDr_V4 :
1151 case Hexagon::MemOPh_SUBr_V4 :
1152 case Hexagon::MemOPh_ANDr_V4 :
1153 case Hexagon::MemOPh_ORr_V4 :
1154 return (0 <= Offset && Offset <= 127);
1155
1156 case Hexagon::MemOPb_ADDi_V4 :
1157 case Hexagon::MemOPb_SUBi_V4 :
1158 case Hexagon::MemOPb_ADDr_V4 :
1159 case Hexagon::MemOPb_SUBr_V4 :
1160 case Hexagon::MemOPb_ANDr_V4 :
1161 case Hexagon::MemOPb_ORr_V4 :
1162 return (0 <= Offset && Offset <= 63);
1163
1164 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1165 // any size. Later pass knows how to handle it.
1166 case Hexagon::STriw_pred:
1167 case Hexagon::LDriw_pred:
1168 return true;
1169
1170 case Hexagon::LOOP0_i:
1171 return isUInt<10>(Offset);
1172
1173 // INLINEASM is very special.
1174 case Hexagon::INLINEASM:
1175 return true;
1176 }
1177
1178 llvm_unreachable("No offset range is defined for this opcode. "
1179 "Please define it in the above switch statement!");
1180 }
1181
1182
1183 //
1184 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1185 //
1186 bool HexagonInstrInfo::
isValidAutoIncImm(const EVT VT,const int Offset) const1187 isValidAutoIncImm(const EVT VT, const int Offset) const {
1188
1189 if (VT == MVT::i64) {
1190 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1191 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1192 (Offset & 0x7) == 0);
1193 }
1194 if (VT == MVT::i32) {
1195 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1196 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1197 (Offset & 0x3) == 0);
1198 }
1199 if (VT == MVT::i16) {
1200 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1201 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1202 (Offset & 0x1) == 0);
1203 }
1204 if (VT == MVT::i8) {
1205 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1206 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1207 }
1208 llvm_unreachable("Not an auto-inc opc!");
1209 }
1210
1211
1212 bool HexagonInstrInfo::
isMemOp(const MachineInstr * MI) const1213 isMemOp(const MachineInstr *MI) const {
1214 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1215
1216 switch (MI->getOpcode())
1217 {
1218 default: return false;
1219 case Hexagon::MemOPw_ADDi_V4 :
1220 case Hexagon::MemOPw_SUBi_V4 :
1221 case Hexagon::MemOPw_ADDr_V4 :
1222 case Hexagon::MemOPw_SUBr_V4 :
1223 case Hexagon::MemOPw_ANDr_V4 :
1224 case Hexagon::MemOPw_ORr_V4 :
1225 case Hexagon::MemOPh_ADDi_V4 :
1226 case Hexagon::MemOPh_SUBi_V4 :
1227 case Hexagon::MemOPh_ADDr_V4 :
1228 case Hexagon::MemOPh_SUBr_V4 :
1229 case Hexagon::MemOPh_ANDr_V4 :
1230 case Hexagon::MemOPh_ORr_V4 :
1231 case Hexagon::MemOPb_ADDi_V4 :
1232 case Hexagon::MemOPb_SUBi_V4 :
1233 case Hexagon::MemOPb_ADDr_V4 :
1234 case Hexagon::MemOPb_SUBr_V4 :
1235 case Hexagon::MemOPb_ANDr_V4 :
1236 case Hexagon::MemOPb_ORr_V4 :
1237 case Hexagon::MemOPb_SETBITi_V4:
1238 case Hexagon::MemOPh_SETBITi_V4:
1239 case Hexagon::MemOPw_SETBITi_V4:
1240 case Hexagon::MemOPb_CLRBITi_V4:
1241 case Hexagon::MemOPh_CLRBITi_V4:
1242 case Hexagon::MemOPw_CLRBITi_V4:
1243 return true;
1244 }
1245 return false;
1246 }
1247
1248
1249 bool HexagonInstrInfo::
isSpillPredRegOp(const MachineInstr * MI) const1250 isSpillPredRegOp(const MachineInstr *MI) const {
1251 switch (MI->getOpcode()) {
1252 default: return false;
1253 case Hexagon::STriw_pred :
1254 case Hexagon::LDriw_pred :
1255 return true;
1256 }
1257 }
1258
isNewValueJumpCandidate(const MachineInstr * MI) const1259 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1260 switch (MI->getOpcode()) {
1261 default: return false;
1262 case Hexagon::CMPEQrr:
1263 case Hexagon::CMPEQri:
1264 case Hexagon::CMPGTrr:
1265 case Hexagon::CMPGTri:
1266 case Hexagon::CMPGTUrr:
1267 case Hexagon::CMPGTUri:
1268 return true;
1269 }
1270 }
1271
1272 bool HexagonInstrInfo::
isConditionalTransfer(const MachineInstr * MI) const1273 isConditionalTransfer (const MachineInstr *MI) const {
1274 switch (MI->getOpcode()) {
1275 default: return false;
1276 case Hexagon::TFR_cPt:
1277 case Hexagon::TFR_cNotPt:
1278 case Hexagon::TFRI_cPt:
1279 case Hexagon::TFRI_cNotPt:
1280 case Hexagon::TFR_cdnPt:
1281 case Hexagon::TFR_cdnNotPt:
1282 case Hexagon::TFRI_cdnPt:
1283 case Hexagon::TFRI_cdnNotPt:
1284 return true;
1285 }
1286 }
1287
isConditionalALU32(const MachineInstr * MI) const1288 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1289 const HexagonRegisterInfo& QRI = getRegisterInfo();
1290 switch (MI->getOpcode())
1291 {
1292 default: return false;
1293 case Hexagon::ADD_ri_cPt:
1294 case Hexagon::ADD_ri_cNotPt:
1295 case Hexagon::ADD_rr_cPt:
1296 case Hexagon::ADD_rr_cNotPt:
1297 case Hexagon::XOR_rr_cPt:
1298 case Hexagon::XOR_rr_cNotPt:
1299 case Hexagon::AND_rr_cPt:
1300 case Hexagon::AND_rr_cNotPt:
1301 case Hexagon::OR_rr_cPt:
1302 case Hexagon::OR_rr_cNotPt:
1303 case Hexagon::SUB_rr_cPt:
1304 case Hexagon::SUB_rr_cNotPt:
1305 case Hexagon::COMBINE_rr_cPt:
1306 case Hexagon::COMBINE_rr_cNotPt:
1307 return true;
1308 case Hexagon::ASLH_cPt_V4:
1309 case Hexagon::ASLH_cNotPt_V4:
1310 case Hexagon::ASRH_cPt_V4:
1311 case Hexagon::ASRH_cNotPt_V4:
1312 case Hexagon::SXTB_cPt_V4:
1313 case Hexagon::SXTB_cNotPt_V4:
1314 case Hexagon::SXTH_cPt_V4:
1315 case Hexagon::SXTH_cNotPt_V4:
1316 case Hexagon::ZXTB_cPt_V4:
1317 case Hexagon::ZXTB_cNotPt_V4:
1318 case Hexagon::ZXTH_cPt_V4:
1319 case Hexagon::ZXTH_cNotPt_V4:
1320 return QRI.Subtarget.hasV4TOps();
1321 }
1322 }
1323
1324 bool HexagonInstrInfo::
isConditionalLoad(const MachineInstr * MI) const1325 isConditionalLoad (const MachineInstr* MI) const {
1326 const HexagonRegisterInfo& QRI = getRegisterInfo();
1327 switch (MI->getOpcode())
1328 {
1329 default: return false;
1330 case Hexagon::LDrid_cPt :
1331 case Hexagon::LDrid_cNotPt :
1332 case Hexagon::LDrid_indexed_cPt :
1333 case Hexagon::LDrid_indexed_cNotPt :
1334 case Hexagon::LDriw_cPt :
1335 case Hexagon::LDriw_cNotPt :
1336 case Hexagon::LDriw_indexed_cPt :
1337 case Hexagon::LDriw_indexed_cNotPt :
1338 case Hexagon::LDrih_cPt :
1339 case Hexagon::LDrih_cNotPt :
1340 case Hexagon::LDrih_indexed_cPt :
1341 case Hexagon::LDrih_indexed_cNotPt :
1342 case Hexagon::LDrib_cPt :
1343 case Hexagon::LDrib_cNotPt :
1344 case Hexagon::LDrib_indexed_cPt :
1345 case Hexagon::LDrib_indexed_cNotPt :
1346 case Hexagon::LDriuh_cPt :
1347 case Hexagon::LDriuh_cNotPt :
1348 case Hexagon::LDriuh_indexed_cPt :
1349 case Hexagon::LDriuh_indexed_cNotPt :
1350 case Hexagon::LDriub_cPt :
1351 case Hexagon::LDriub_cNotPt :
1352 case Hexagon::LDriub_indexed_cPt :
1353 case Hexagon::LDriub_indexed_cNotPt :
1354 return true;
1355 case Hexagon::POST_LDrid_cPt :
1356 case Hexagon::POST_LDrid_cNotPt :
1357 case Hexagon::POST_LDriw_cPt :
1358 case Hexagon::POST_LDriw_cNotPt :
1359 case Hexagon::POST_LDrih_cPt :
1360 case Hexagon::POST_LDrih_cNotPt :
1361 case Hexagon::POST_LDrib_cPt :
1362 case Hexagon::POST_LDrib_cNotPt :
1363 case Hexagon::POST_LDriuh_cPt :
1364 case Hexagon::POST_LDriuh_cNotPt :
1365 case Hexagon::POST_LDriub_cPt :
1366 case Hexagon::POST_LDriub_cNotPt :
1367 return QRI.Subtarget.hasV4TOps();
1368 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1369 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1370 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1371 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1372 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1373 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1374 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1375 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1376 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1377 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1378 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1379 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1380 return QRI.Subtarget.hasV4TOps();
1381 }
1382 }
1383
1384 // Returns true if an instruction is a conditional store.
1385 //
1386 // Note: It doesn't include conditional new-value stores as they can't be
1387 // converted to .new predicate.
1388 //
1389 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1390 // ^ ^
1391 // / \ (not OK. it will cause new-value store to be
1392 // / X conditional on p0.new while R2 producer is
1393 // / \ on p0)
1394 // / \.
1395 // p.new store p.old NV store
1396 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1397 // ^ ^
1398 // \ /
1399 // \ /
1400 // \ /
1401 // p.old store
1402 // [if (p0)memw(R0+#0)=R2]
1403 //
1404 // The above diagram shows the steps involoved in the conversion of a predicated
1405 // store instruction to its .new predicated new-value form.
1406 //
1407 // The following set of instructions further explains the scenario where
1408 // conditional new-value store becomes invalid when promoted to .new predicate
1409 // form.
1410 //
1411 // { 1) if (p0) r0 = add(r1, r2)
1412 // 2) p0 = cmp.eq(r3, #0) }
1413 //
1414 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1415 // the first two instructions because in instr 1, r0 is conditional on old value
1416 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1417 // is not valid for new-value stores.
1418 bool HexagonInstrInfo::
isConditionalStore(const MachineInstr * MI) const1419 isConditionalStore (const MachineInstr* MI) const {
1420 const HexagonRegisterInfo& QRI = getRegisterInfo();
1421 switch (MI->getOpcode())
1422 {
1423 default: return false;
1424 case Hexagon::STrib_imm_cPt_V4 :
1425 case Hexagon::STrib_imm_cNotPt_V4 :
1426 case Hexagon::STrib_indexed_shl_cPt_V4 :
1427 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
1428 case Hexagon::STrib_cPt :
1429 case Hexagon::STrib_cNotPt :
1430 case Hexagon::POST_STbri_cPt :
1431 case Hexagon::POST_STbri_cNotPt :
1432 case Hexagon::STrid_indexed_cPt :
1433 case Hexagon::STrid_indexed_cNotPt :
1434 case Hexagon::STrid_indexed_shl_cPt_V4 :
1435 case Hexagon::POST_STdri_cPt :
1436 case Hexagon::POST_STdri_cNotPt :
1437 case Hexagon::STrih_cPt :
1438 case Hexagon::STrih_cNotPt :
1439 case Hexagon::STrih_indexed_cPt :
1440 case Hexagon::STrih_indexed_cNotPt :
1441 case Hexagon::STrih_imm_cPt_V4 :
1442 case Hexagon::STrih_imm_cNotPt_V4 :
1443 case Hexagon::STrih_indexed_shl_cPt_V4 :
1444 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
1445 case Hexagon::POST_SThri_cPt :
1446 case Hexagon::POST_SThri_cNotPt :
1447 case Hexagon::STriw_cPt :
1448 case Hexagon::STriw_cNotPt :
1449 case Hexagon::STriw_indexed_cPt :
1450 case Hexagon::STriw_indexed_cNotPt :
1451 case Hexagon::STriw_imm_cPt_V4 :
1452 case Hexagon::STriw_imm_cNotPt_V4 :
1453 case Hexagon::STriw_indexed_shl_cPt_V4 :
1454 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
1455 case Hexagon::POST_STwri_cPt :
1456 case Hexagon::POST_STwri_cNotPt :
1457 return QRI.Subtarget.hasV4TOps();
1458
1459 // V4 global address store before promoting to dot new.
1460 case Hexagon::STd_GP_cPt_V4 :
1461 case Hexagon::STd_GP_cNotPt_V4 :
1462 case Hexagon::STb_GP_cPt_V4 :
1463 case Hexagon::STb_GP_cNotPt_V4 :
1464 case Hexagon::STh_GP_cPt_V4 :
1465 case Hexagon::STh_GP_cNotPt_V4 :
1466 case Hexagon::STw_GP_cPt_V4 :
1467 case Hexagon::STw_GP_cNotPt_V4 :
1468 return QRI.Subtarget.hasV4TOps();
1469
1470 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1471 // from the "Conditional Store" list. Because a predicated new value store
1472 // would NOT be promoted to a double dot new store. See diagram below:
1473 // This function returns yes for those stores that are predicated but not
1474 // yet promoted to predicate dot new instructions.
1475 //
1476 // +---------------------+
1477 // /-----| if (p0) memw(..)=r0 |---------\~
1478 // || +---------------------+ ||
1479 // promote || /\ /\ || promote
1480 // || /||\ /||\ ||
1481 // \||/ demote || \||/
1482 // \/ || || \/
1483 // +-------------------------+ || +-------------------------+
1484 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1485 // +-------------------------+ || +-------------------------+
1486 // || || ||
1487 // || demote \||/
1488 // promote || \/ NOT possible
1489 // || || /\~
1490 // \||/ || /||\~
1491 // \/ || ||
1492 // +-----------------------------+
1493 // | if (p0.new) memw(..)=r0.new |
1494 // +-----------------------------+
1495 // Double Dot New Store
1496 //
1497 }
1498 }
1499
1500
isNewValueJump(const MachineInstr * MI) const1501 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1502 if (isNewValue(MI) && isBranch(MI))
1503 return true;
1504 return false;
1505 }
1506
isPostIncrement(const MachineInstr * MI) const1507 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1508 return (getAddrMode(MI) == HexagonII::PostInc);
1509 }
1510
isNewValue(const MachineInstr * MI) const1511 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1512 const uint64_t F = MI->getDesc().TSFlags;
1513 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1514 }
1515
1516 // Returns true, if any one of the operands is a dot new
1517 // insn, whether it is predicated dot new or register dot new.
isDotNewInst(const MachineInstr * MI) const1518 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1519 return (isNewValueInst(MI) ||
1520 (isPredicated(MI) && isPredicatedNew(MI)));
1521 }
1522
1523 // Returns the most basic instruction for the .new predicated instructions and
1524 // new-value stores.
1525 // For example, all of the following instructions will be converted back to the
1526 // same instruction:
1527 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1528 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1529 // 3) if (p0.new) memw(R0+#0) = R1 --->
1530 //
1531
GetDotOldOp(const int opc) const1532 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1533 int NewOp = opc;
1534 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1535 NewOp = Hexagon::getPredOldOpcode(NewOp);
1536 if (NewOp < 0)
1537 assert(0 && "Couldn't change predicate new instruction to its old form.");
1538 }
1539
1540 if (isNewValueStore(NewOp)) { // Convert into non new-value format
1541 NewOp = Hexagon::getNonNVStore(NewOp);
1542 if (NewOp < 0)
1543 assert(0 && "Couldn't change new-value store to its old form.");
1544 }
1545 return NewOp;
1546 }
1547
1548 // Return the new value instruction for a given store.
GetDotNewOp(const MachineInstr * MI) const1549 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1550 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1551 if (NVOpcode >= 0) // Valid new-value store instruction.
1552 return NVOpcode;
1553
1554 switch (MI->getOpcode()) {
1555 default: llvm_unreachable("Unknown .new type");
1556 // store new value byte
1557 case Hexagon::STrib_shl_V4:
1558 return Hexagon::STrib_shl_nv_V4;
1559
1560 case Hexagon::STrih_shl_V4:
1561 return Hexagon::STrih_shl_nv_V4;
1562
1563 case Hexagon::STriw_f:
1564 return Hexagon::STriw_nv_V4;
1565
1566 case Hexagon::STriw_indexed_f:
1567 return Hexagon::STriw_indexed_nv_V4;
1568
1569 case Hexagon::STriw_shl_V4:
1570 return Hexagon::STriw_shl_nv_V4;
1571
1572 }
1573 return 0;
1574 }
1575
1576 // Return .new predicate version for an instruction.
GetDotNewPredOp(MachineInstr * MI,const MachineBranchProbabilityInfo * MBPI) const1577 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1578 const MachineBranchProbabilityInfo
1579 *MBPI) const {
1580
1581 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1582 if (NewOpcode >= 0) // Valid predicate new instruction
1583 return NewOpcode;
1584
1585 switch (MI->getOpcode()) {
1586 default: llvm_unreachable("Unknown .new type");
1587 // Condtional Jumps
1588 case Hexagon::JMP_t:
1589 case Hexagon::JMP_f:
1590 return getDotNewPredJumpOp(MI, MBPI);
1591
1592 case Hexagon::JMPR_t:
1593 return Hexagon::JMPR_tnew_tV3;
1594
1595 case Hexagon::JMPR_f:
1596 return Hexagon::JMPR_fnew_tV3;
1597
1598 case Hexagon::JMPret_t:
1599 return Hexagon::JMPret_tnew_tV3;
1600
1601 case Hexagon::JMPret_f:
1602 return Hexagon::JMPret_fnew_tV3;
1603
1604
1605 // Conditional combine
1606 case Hexagon::COMBINE_rr_cPt :
1607 return Hexagon::COMBINE_rr_cdnPt;
1608 case Hexagon::COMBINE_rr_cNotPt :
1609 return Hexagon::COMBINE_rr_cdnNotPt;
1610 }
1611 }
1612
1613
getAddrMode(const MachineInstr * MI) const1614 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1615 const uint64_t F = MI->getDesc().TSFlags;
1616
1617 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1618 }
1619
1620 /// immediateExtend - Changes the instruction in place to one using an immediate
1621 /// extender.
immediateExtend(MachineInstr * MI) const1622 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1623 assert((isExtendable(MI)||isConstExtended(MI)) &&
1624 "Instruction must be extendable");
1625 // Find which operand is extendable.
1626 short ExtOpNum = getCExtOpNum(MI);
1627 MachineOperand &MO = MI->getOperand(ExtOpNum);
1628 // This needs to be something we understand.
1629 assert((MO.isMBB() || MO.isImm()) &&
1630 "Branch with unknown extendable field type");
1631 // Mark given operand as extended.
1632 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1633 }
1634
1635 DFAPacketizer *HexagonInstrInfo::
CreateTargetScheduleState(const TargetMachine * TM,const ScheduleDAG * DAG) const1636 CreateTargetScheduleState(const TargetMachine *TM,
1637 const ScheduleDAG *DAG) const {
1638 const InstrItineraryData *II = TM->getInstrItineraryData();
1639 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
1640 }
1641
isSchedulingBoundary(const MachineInstr * MI,const MachineBasicBlock * MBB,const MachineFunction & MF) const1642 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1643 const MachineBasicBlock *MBB,
1644 const MachineFunction &MF) const {
1645 // Debug info is never a scheduling boundary. It's necessary to be explicit
1646 // due to the special treatment of IT instructions below, otherwise a
1647 // dbg_value followed by an IT will result in the IT instruction being
1648 // considered a scheduling hazard, which is wrong. It should be the actual
1649 // instruction preceding the dbg_value instruction(s), just like it is
1650 // when debug info is not present.
1651 if (MI->isDebugValue())
1652 return false;
1653
1654 // Terminators and labels can't be scheduled around.
1655 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
1656 return true;
1657
1658 return false;
1659 }
1660
isConstExtended(MachineInstr * MI) const1661 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1662
1663 // Constant extenders are allowed only for V4 and above.
1664 if (!Subtarget.hasV4TOps())
1665 return false;
1666
1667 const uint64_t F = MI->getDesc().TSFlags;
1668 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1669 if (isExtended) // Instruction must be extended.
1670 return true;
1671
1672 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1673 & HexagonII::ExtendableMask;
1674 if (!isExtendable)
1675 return false;
1676
1677 short ExtOpNum = getCExtOpNum(MI);
1678 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1679 // Use MO operand flags to determine if MO
1680 // has the HMOTF_ConstExtended flag set.
1681 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1682 return true;
1683 // If this is a Machine BB address we are talking about, and it is
1684 // not marked as extended, say so.
1685 if (MO.isMBB())
1686 return false;
1687
1688 // We could be using an instruction with an extendable immediate and shoehorn
1689 // a global address into it. If it is a global address it will be constant
1690 // extended. We do this for COMBINE.
1691 // We currently only handle isGlobal() because it is the only kind of
1692 // object we are going to end up with here for now.
1693 // In the future we probably should add isSymbol(), etc.
1694 if (MO.isGlobal() || MO.isSymbol())
1695 return true;
1696
1697 // If the extendable operand is not 'Immediate' type, the instruction should
1698 // have 'isExtended' flag set.
1699 assert(MO.isImm() && "Extendable operand must be Immediate type");
1700
1701 int MinValue = getMinValue(MI);
1702 int MaxValue = getMaxValue(MI);
1703 int ImmValue = MO.getImm();
1704
1705 return (ImmValue < MinValue || ImmValue > MaxValue);
1706 }
1707
1708 // Returns the opcode to use when converting MI, which is a conditional jump,
1709 // into a conditional instruction which uses the .new value of the predicate.
1710 // We also use branch probabilities to add a hint to the jump.
1711 int
getDotNewPredJumpOp(MachineInstr * MI,const MachineBranchProbabilityInfo * MBPI) const1712 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1713 const
1714 MachineBranchProbabilityInfo *MBPI) const {
1715
1716 // We assume that block can have at most two successors.
1717 bool taken = false;
1718 MachineBasicBlock *Src = MI->getParent();
1719 MachineOperand *BrTarget = &MI->getOperand(1);
1720 MachineBasicBlock *Dst = BrTarget->getMBB();
1721
1722 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1723 if (Prediction >= BranchProbability(1,2))
1724 taken = true;
1725
1726 switch (MI->getOpcode()) {
1727 case Hexagon::JMP_t:
1728 return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
1729 case Hexagon::JMP_f:
1730 return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
1731
1732 default:
1733 llvm_unreachable("Unexpected jump instruction.");
1734 }
1735 }
1736 // Returns true if a particular operand is extendable for an instruction.
isOperandExtended(const MachineInstr * MI,unsigned short OperandNum) const1737 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1738 unsigned short OperandNum) const {
1739 // Constant extenders are allowed only for V4 and above.
1740 if (!Subtarget.hasV4TOps())
1741 return false;
1742
1743 const uint64_t F = MI->getDesc().TSFlags;
1744
1745 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1746 == OperandNum;
1747 }
1748
1749 // Returns Operand Index for the constant extended instruction.
getCExtOpNum(const MachineInstr * MI) const1750 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1751 const uint64_t F = MI->getDesc().TSFlags;
1752 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1753 }
1754
1755 // Returns the min value that doesn't need to be extended.
getMinValue(const MachineInstr * MI) const1756 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1757 const uint64_t F = MI->getDesc().TSFlags;
1758 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1759 & HexagonII::ExtentSignedMask;
1760 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1761 & HexagonII::ExtentBitsMask;
1762
1763 if (isSigned) // if value is signed
1764 return -1 << (bits - 1);
1765 else
1766 return 0;
1767 }
1768
1769 // Returns the max value that doesn't need to be extended.
getMaxValue(const MachineInstr * MI) const1770 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1771 const uint64_t F = MI->getDesc().TSFlags;
1772 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1773 & HexagonII::ExtentSignedMask;
1774 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1775 & HexagonII::ExtentBitsMask;
1776
1777 if (isSigned) // if value is signed
1778 return ~(-1 << (bits - 1));
1779 else
1780 return ~(-1 << bits);
1781 }
1782
1783 // Returns true if an instruction can be converted into a non-extended
1784 // equivalent instruction.
NonExtEquivalentExists(const MachineInstr * MI) const1785 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1786
1787 short NonExtOpcode;
1788 // Check if the instruction has a register form that uses register in place
1789 // of the extended operand, if so return that as the non-extended form.
1790 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1791 return true;
1792
1793 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1794 // Check addressing mode and retreive non-ext equivalent instruction.
1795
1796 switch (getAddrMode(MI)) {
1797 case HexagonII::Absolute :
1798 // Load/store with absolute addressing mode can be converted into
1799 // base+offset mode.
1800 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1801 break;
1802 case HexagonII::BaseImmOffset :
1803 // Load/store with base+offset addressing mode can be converted into
1804 // base+register offset addressing mode. However left shift operand should
1805 // be set to 0.
1806 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1807 break;
1808 default:
1809 return false;
1810 }
1811 if (NonExtOpcode < 0)
1812 return false;
1813 return true;
1814 }
1815 return false;
1816 }
1817
1818 // Returns opcode of the non-extended equivalent instruction.
getNonExtOpcode(const MachineInstr * MI) const1819 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1820
1821 // Check if the instruction has a register form that uses register in place
1822 // of the extended operand, if so return that as the non-extended form.
1823 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1824 if (NonExtOpcode >= 0)
1825 return NonExtOpcode;
1826
1827 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1828 // Check addressing mode and retreive non-ext equivalent instruction.
1829 switch (getAddrMode(MI)) {
1830 case HexagonII::Absolute :
1831 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1832 case HexagonII::BaseImmOffset :
1833 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1834 default:
1835 return -1;
1836 }
1837 }
1838 return -1;
1839 }
1840
PredOpcodeHasJMP_c(Opcode_t Opcode) const1841 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1842 return (Opcode == Hexagon::JMP_t) ||
1843 (Opcode == Hexagon::JMP_f) ||
1844 (Opcode == Hexagon::JMP_tnew_t) ||
1845 (Opcode == Hexagon::JMP_fnew_t) ||
1846 (Opcode == Hexagon::JMP_tnew_nt) ||
1847 (Opcode == Hexagon::JMP_fnew_nt);
1848 }
1849
PredOpcodeHasNot(Opcode_t Opcode) const1850 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1851 return (Opcode == Hexagon::JMP_f) ||
1852 (Opcode == Hexagon::JMP_fnew_t) ||
1853 (Opcode == Hexagon::JMP_fnew_nt);
1854 }
1855