1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMBaseInfo.h"
15 #include "ARMELFStreamer.h"
16 #include "ARMMCAsmInfo.h"
17 #include "ARMMCTargetDesc.h"
18 #include "InstPrinter/ARMInstPrinter.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/MC/MCCodeGenInfo.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28
29 #define GET_REGINFO_MC_DESC
30 #include "ARMGenRegisterInfo.inc"
31
32 #define GET_INSTRINFO_MC_DESC
33 #include "ARMGenInstrInfo.inc"
34
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "ARMGenSubtargetInfo.inc"
37
38 using namespace llvm;
39
ParseARMTriple(StringRef TT,StringRef CPU)40 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
41 Triple triple(TT);
42
43 // Set the boolean corresponding to the current target triple, or the default
44 // if one cannot be determined, to true.
45 unsigned Len = TT.size();
46 unsigned Idx = 0;
47
48 // FIXME: Enhance Triple helper class to extract ARM version.
49 bool isThumb = false;
50 if (Len >= 5 && TT.substr(0, 4) == "armv")
51 Idx = 4;
52 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
53 isThumb = true;
54 if (Len >= 7 && TT[5] == 'v')
55 Idx = 6;
56 }
57
58 bool NoCPU = CPU == "generic" || CPU.empty();
59 std::string ARMArchFeature;
60 if (Idx) {
61 unsigned SubVer = TT[Idx];
62 if (SubVer == '8') {
63 // FIXME: Parse v8 features
64 ARMArchFeature = "+v8";
65 } else if (SubVer == '7') {
66 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
67 isThumb = true;
68 if (NoCPU)
69 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
70 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
71 else
72 // Use CPU to figure out the exact features.
73 ARMArchFeature = "+v7";
74 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
75 if (NoCPU)
76 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
77 // FeatureT2XtPk, FeatureMClass
78 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
79 else
80 // Use CPU to figure out the exact features.
81 ARMArchFeature = "+v7";
82 } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
83 if (NoCPU)
84 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
85 // Swift
86 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
87 else
88 // Use CPU to figure out the exact features.
89 ARMArchFeature = "+v7";
90 } else {
91 // v7 CPUs have lots of different feature sets. If no CPU is specified,
92 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
93 // the "minimum" feature set and use CPU string to figure out the exact
94 // features.
95 if (NoCPU)
96 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
97 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
98 else
99 // Use CPU to figure out the exact features.
100 ARMArchFeature = "+v7";
101 }
102 } else if (SubVer == '6') {
103 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
104 ARMArchFeature = "+v6t2";
105 else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
106 isThumb = true;
107 if (NoCPU)
108 // v6m: FeatureNoARM, FeatureMClass
109 ARMArchFeature = "+v6,+noarm,+mclass";
110 else
111 ARMArchFeature = "+v6";
112 } else
113 ARMArchFeature = "+v6";
114 } else if (SubVer == '5') {
115 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
116 ARMArchFeature = "+v5te";
117 else
118 ARMArchFeature = "+v5t";
119 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
120 ARMArchFeature = "+v4t";
121 }
122
123 if (isThumb) {
124 if (ARMArchFeature.empty())
125 ARMArchFeature = "+thumb-mode";
126 else
127 ARMArchFeature += ",+thumb-mode";
128 }
129
130 if (triple.isOSNaCl()) {
131 if (ARMArchFeature.empty())
132 ARMArchFeature = "+nacl-trap";
133 else
134 ARMArchFeature += ",+nacl-trap";
135 }
136
137 return ARMArchFeature;
138 }
139
createARMMCSubtargetInfo(StringRef TT,StringRef CPU,StringRef FS)140 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
141 StringRef FS) {
142 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
143 if (!FS.empty()) {
144 if (!ArchFS.empty())
145 ArchFS = ArchFS + "," + FS.str();
146 else
147 ArchFS = FS;
148 }
149
150 MCSubtargetInfo *X = new MCSubtargetInfo();
151 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
152 return X;
153 }
154
createARMMCInstrInfo()155 static MCInstrInfo *createARMMCInstrInfo() {
156 MCInstrInfo *X = new MCInstrInfo();
157 InitARMMCInstrInfo(X);
158 return X;
159 }
160
createARMMCRegisterInfo(StringRef Triple)161 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
162 MCRegisterInfo *X = new MCRegisterInfo();
163 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
164 return X;
165 }
166
createARMMCAsmInfo(const MCRegisterInfo & MRI,StringRef TT)167 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
168 Triple TheTriple(TT);
169
170 if (TheTriple.isOSDarwin())
171 return new ARMMCAsmInfoDarwin();
172
173 return new ARMELFMCAsmInfo();
174 }
175
createARMMCCodeGenInfo(StringRef TT,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)176 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
177 CodeModel::Model CM,
178 CodeGenOpt::Level OL) {
179 MCCodeGenInfo *X = new MCCodeGenInfo();
180 if (RM == Reloc::Default) {
181 Triple TheTriple(TT);
182 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
183 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
184 }
185 X->InitMCCodeGenInfo(RM, CM, OL);
186 return X;
187 }
188
189 // This is duplicated code. Refactor this.
createMCStreamer(const Target & T,StringRef TT,MCContext & Ctx,MCAsmBackend & MAB,raw_ostream & OS,MCCodeEmitter * Emitter,bool RelaxAll,bool NoExecStack)190 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
191 MCContext &Ctx, MCAsmBackend &MAB,
192 raw_ostream &OS,
193 MCCodeEmitter *Emitter,
194 bool RelaxAll,
195 bool NoExecStack) {
196 Triple TheTriple(TT);
197
198 if (TheTriple.isOSDarwin())
199 return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
200
201 if (TheTriple.isOSWindows()) {
202 llvm_unreachable("ARM does not support Windows COFF format");
203 }
204
205 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
206 TheTriple.getArch() == Triple::thumb);
207 }
208
createARMMCInstPrinter(const Target & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI,const MCSubtargetInfo & STI)209 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
210 unsigned SyntaxVariant,
211 const MCAsmInfo &MAI,
212 const MCInstrInfo &MII,
213 const MCRegisterInfo &MRI,
214 const MCSubtargetInfo &STI) {
215 if (SyntaxVariant == 0)
216 return new ARMInstPrinter(MAI, MII, MRI, STI);
217 return 0;
218 }
219
createARMMCRelocationInfo(StringRef TT,MCContext & Ctx)220 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
221 MCContext &Ctx) {
222 Triple TheTriple(TT);
223 if (TheTriple.isEnvironmentMachO())
224 return createARMMachORelocationInfo(Ctx);
225 // Default to the stock relocation info.
226 return llvm::createMCRelocationInfo(TT, Ctx);
227 }
228
229 namespace {
230
231 class ARMMCInstrAnalysis : public MCInstrAnalysis {
232 public:
ARMMCInstrAnalysis(const MCInstrInfo * Info)233 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
234
isUnconditionalBranch(const MCInst & Inst) const235 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
236 // BCCs with the "always" predicate are unconditional branches.
237 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
238 return true;
239 return MCInstrAnalysis::isUnconditionalBranch(Inst);
240 }
241
isConditionalBranch(const MCInst & Inst) const242 virtual bool isConditionalBranch(const MCInst &Inst) const {
243 // BCCs with the "always" predicate are unconditional branches.
244 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
245 return false;
246 return MCInstrAnalysis::isConditionalBranch(Inst);
247 }
248
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const249 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
250 uint64_t Size, uint64_t &Target) const {
251 // We only handle PCRel branches for now.
252 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
253 return false;
254
255 int64_t Imm = Inst.getOperand(0).getImm();
256 // FIXME: This is not right for thumb.
257 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
258 return true;
259 }
260 };
261
262 }
263
createARMMCInstrAnalysis(const MCInstrInfo * Info)264 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
265 return new ARMMCInstrAnalysis(Info);
266 }
267
268 // Force static initialization.
LLVMInitializeARMTargetMC()269 extern "C" void LLVMInitializeARMTargetMC() {
270 // Register the MC asm info.
271 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
272 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
273
274 // Register the MC codegen info.
275 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
276 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
277
278 // Register the MC instruction info.
279 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
280 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
281
282 // Register the MC register info.
283 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
284 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
285
286 // Register the MC subtarget info.
287 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
288 ARM_MC::createARMMCSubtargetInfo);
289 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
290 ARM_MC::createARMMCSubtargetInfo);
291
292 // Register the MC instruction analyzer.
293 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
294 createARMMCInstrAnalysis);
295 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
296 createARMMCInstrAnalysis);
297
298 // Register the MC Code Emitter
299 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
300 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
301
302 // Register the asm backend.
303 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
304 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
305
306 // Register the object streamer.
307 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
308 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
309
310 // Register the MCInstPrinter.
311 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
312 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
313
314 // Register the MC relocation info.
315 TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
316 createARMMCRelocationInfo);
317 TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
318 createARMMCRelocationInfo);
319 }
320