1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines an instruction selector for the XCore target.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "XCore.h"
15 #include "XCoreTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DerivedTypes.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetLowering.h"
33 using namespace llvm;
34
35 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
36 /// instructions for SelectionDAG operations.
37 ///
38 namespace {
39 class XCoreDAGToDAGISel : public SelectionDAGISel {
40 const XCoreSubtarget &Subtarget;
41
42 public:
XCoreDAGToDAGISel(XCoreTargetMachine & TM,CodeGenOpt::Level OptLevel)43 XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
44 : SelectionDAGISel(TM, OptLevel),
45 Subtarget(*TM.getSubtargetImpl()) { }
46
47 SDNode *Select(SDNode *N);
48 SDNode *SelectBRIND(SDNode *N);
49
50 /// getI32Imm - Return a target constant with the specified value, of type
51 /// i32.
getI32Imm(unsigned Imm)52 inline SDValue getI32Imm(unsigned Imm) {
53 return CurDAG->getTargetConstant(Imm, MVT::i32);
54 }
55
immMskBitp(SDNode * inN) const56 inline bool immMskBitp(SDNode *inN) const {
57 ConstantSDNode *N = cast<ConstantSDNode>(inN);
58 uint32_t value = (uint32_t)N->getZExtValue();
59 if (!isMask_32(value)) {
60 return false;
61 }
62 int msksize = 32 - countLeadingZeros(value);
63 return (msksize >= 1 && msksize <= 8) ||
64 msksize == 16 || msksize == 24 || msksize == 32;
65 }
66
67 // Complex Pattern Selectors.
68 bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
69
getPassName() const70 virtual const char *getPassName() const {
71 return "XCore DAG->DAG Pattern Instruction Selection";
72 }
73
74 // Include the pieces autogenerated from the target description.
75 #include "XCoreGenDAGISel.inc"
76 };
77 } // end anonymous namespace
78
79 /// createXCoreISelDag - This pass converts a legalized DAG into a
80 /// XCore-specific DAG, ready for instruction scheduling.
81 ///
createXCoreISelDag(XCoreTargetMachine & TM,CodeGenOpt::Level OptLevel)82 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM,
83 CodeGenOpt::Level OptLevel) {
84 return new XCoreDAGToDAGISel(TM, OptLevel);
85 }
86
SelectADDRspii(SDValue Addr,SDValue & Base,SDValue & Offset)87 bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
88 SDValue &Offset) {
89 FrameIndexSDNode *FIN = 0;
90 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
91 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
92 Offset = CurDAG->getTargetConstant(0, MVT::i32);
93 return true;
94 }
95 if (Addr.getOpcode() == ISD::ADD) {
96 ConstantSDNode *CN = 0;
97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
99 && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
100 // Constant positive word offset from frame index
101 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
102 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
103 return true;
104 }
105 }
106 return false;
107 }
108
Select(SDNode * N)109 SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
110 SDLoc dl(N);
111 switch (N->getOpcode()) {
112 default: break;
113 case ISD::Constant: {
114 uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
115 if (immMskBitp(N)) {
116 // Transformation function: get the size of a mask
117 // Look for the first non-zero bit
118 SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val));
119 return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
120 MVT::i32, MskSize);
121 }
122 else if (!isUInt<16>(Val)) {
123 SDValue CPIdx =
124 CurDAG->getTargetConstantPool(ConstantInt::get(
125 Type::getInt32Ty(*CurDAG->getContext()), Val),
126 getTargetLowering()->getPointerTy());
127 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
128 MVT::Other, CPIdx,
129 CurDAG->getEntryNode());
130 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
131 MemOp[0] = MF->getMachineMemOperand(
132 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 4, 4);
133 cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1);
134 return node;
135 }
136 break;
137 }
138 case XCoreISD::LADD: {
139 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
140 N->getOperand(2) };
141 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
142 Ops);
143 }
144 case XCoreISD::LSUB: {
145 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
146 N->getOperand(2) };
147 return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
148 Ops);
149 }
150 case XCoreISD::MACCU: {
151 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
152 N->getOperand(2), N->getOperand(3) };
153 return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
154 Ops);
155 }
156 case XCoreISD::MACCS: {
157 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
158 N->getOperand(2), N->getOperand(3) };
159 return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
160 Ops);
161 }
162 case XCoreISD::LMUL: {
163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
164 N->getOperand(2), N->getOperand(3) };
165 return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
166 Ops);
167 }
168 case XCoreISD::CRC8: {
169 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
170 return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32,
171 Ops);
172 }
173 case ISD::BRIND:
174 if (SDNode *ResNode = SelectBRIND(N))
175 return ResNode;
176 break;
177 // Other cases are autogenerated.
178 }
179 return SelectCode(N);
180 }
181
182 /// Given a chain return a new chain where any appearance of Old is replaced
183 /// by New. There must be at most one instruction between Old and Chain and
184 /// this instruction must be a TokenFactor. Returns an empty SDValue if
185 /// these conditions don't hold.
186 static SDValue
replaceInChain(SelectionDAG * CurDAG,SDValue Chain,SDValue Old,SDValue New)187 replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New)
188 {
189 if (Chain == Old)
190 return New;
191 if (Chain->getOpcode() != ISD::TokenFactor)
192 return SDValue();
193 SmallVector<SDValue, 8> Ops;
194 bool found = false;
195 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) {
196 if (Chain->getOperand(i) == Old) {
197 Ops.push_back(New);
198 found = true;
199 } else {
200 Ops.push_back(Chain->getOperand(i));
201 }
202 }
203 if (!found)
204 return SDValue();
205 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
206 &Ops[0], Ops.size());
207 }
208
SelectBRIND(SDNode * N)209 SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) {
210 SDLoc dl(N);
211 // (brind (int_xcore_checkevent (addr)))
212 SDValue Chain = N->getOperand(0);
213 SDValue Addr = N->getOperand(1);
214 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
215 return 0;
216 unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
217 if (IntNo != Intrinsic::xcore_checkevent)
218 return 0;
219 SDValue nextAddr = Addr->getOperand(2);
220 SDValue CheckEventChainOut(Addr.getNode(), 1);
221 if (!CheckEventChainOut.use_empty()) {
222 // If the chain out of the checkevent intrinsic is an operand of the
223 // indirect branch or used in a TokenFactor which is the operand of the
224 // indirect branch then build a new chain which uses the chain coming into
225 // the checkevent intrinsic instead.
226 SDValue CheckEventChainIn = Addr->getOperand(0);
227 SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut,
228 CheckEventChainIn);
229 if (!NewChain.getNode())
230 return 0;
231 Chain = NewChain;
232 }
233 // Enable events on the thread using setsr 1 and then disable them immediately
234 // after with clrsr 1. If any resources owned by the thread are ready an event
235 // will be taken. If no resource is ready we branch to the address which was
236 // the operand to the checkevent intrinsic.
237 SDValue constOne = getI32Imm(1);
238 SDValue Glue =
239 SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
240 constOne, Chain), 0);
241 Glue =
242 SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue,
243 constOne, Glue), 0);
244 if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
245 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
246 return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other,
247 nextAddr->getOperand(0), Glue);
248 }
249 return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue);
250 }
251