1 /*
2 * QEMU Common PCI Host bridge configuration data space access routines.
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 /* Worker routines for a PCI host controller that uses an {address,data}
26 register pair to access PCI configuration space. */
27
28 /* debug PCI */
29 //#define DEBUG_PCI
30
31 #ifdef DEBUG_PCI
32 #define PCI_DPRINTF(fmt, ...) \
33 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
34 #else
35 #define PCI_DPRINTF(fmt, ...)
36 #endif
37 struct PCIHostState {
38 uint32_t config_reg;
39 PCIBus *bus;
40 };
41
pci_host_data_writeb(void * opaque,pci_addr_t addr,uint32_t val)42 static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val)
43 {
44 PCIHostState *s = opaque;
45
46 PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n",
47 (target_phys_addr_t)addr, val);
48 if (s->config_reg & (1u << 31))
49 pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);
50 }
51
pci_host_data_writew(void * opaque,pci_addr_t addr,uint32_t val)52 static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val)
53 {
54 PCIHostState *s = opaque;
55 #ifdef TARGET_WORDS_BIGENDIAN
56 val = bswap16(val);
57 #endif
58 PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n",
59 (target_phys_addr_t)addr, val);
60 if (s->config_reg & (1u << 31))
61 pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);
62 }
63
pci_host_data_writel(void * opaque,pci_addr_t addr,uint32_t val)64 static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val)
65 {
66 PCIHostState *s = opaque;
67 #ifdef TARGET_WORDS_BIGENDIAN
68 val = bswap32(val);
69 #endif
70 PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n",
71 (target_phys_addr_t)addr, val);
72 if (s->config_reg & (1u << 31))
73 pci_data_write(s->bus, s->config_reg, val, 4);
74 }
75
pci_host_data_readb(void * opaque,pci_addr_t addr)76 static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr)
77 {
78 PCIHostState *s = opaque;
79 uint32_t val;
80
81 if (!(s->config_reg & (1 << 31)))
82 return 0xff;
83 val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1);
84 PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n",
85 (target_phys_addr_t)addr, val);
86 return val;
87 }
88
pci_host_data_readw(void * opaque,pci_addr_t addr)89 static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr)
90 {
91 PCIHostState *s = opaque;
92 uint32_t val;
93 if (!(s->config_reg & (1 << 31)))
94 return 0xffff;
95 val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);
96 PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n",
97 (target_phys_addr_t)addr, val);
98 #ifdef TARGET_WORDS_BIGENDIAN
99 val = bswap16(val);
100 #endif
101 return val;
102 }
103
pci_host_data_readl(void * opaque,pci_addr_t addr)104 static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr)
105 {
106 PCIHostState *s = opaque;
107 uint32_t val;
108 if (!(s->config_reg & (1 << 31)))
109 return 0xffffffff;
110 val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);
111 PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n",
112 (target_phys_addr_t)addr, val);
113 #ifdef TARGET_WORDS_BIGENDIAN
114 val = bswap32(val);
115 #endif
116 return val;
117 }
118