| /art/compiler/dex/quick/mips/ |
| D | mips_lir.h | 145 INVALID_SREG, INVALID_SREG}
147 INVALID_REG, INVALID_SREG, INVALID_SREG}
149 r_RESULT1, INVALID_SREG, INVALID_SREG}
151 r_FRESULT1, INVALID_SREG, INVALID_SREG}
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| D | int_mips.cc | 462 LoadBaseDispWide(reg_ptr, 0, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); in GenArrayGet()
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| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 325 INVALID_SREG, INVALID_SREG}; in GenAddLong()
341 INVALID_SREG, INVALID_SREG}; in GenSubLong()
357 INVALID_SREG, INVALID_SREG}; in GenAndLong()
373 INVALID_SREG, INVALID_SREG}; in GenOrLong()
389 INVALID_SREG, INVALID_SREG}; in GenXorLong()
402 INVALID_SREG, INVALID_SREG}; in GenNegLong()
451 rl_result.high_reg, size, INVALID_SREG); in GenArrayGet()
458 INVALID_SREG); in GenArrayGet()
500 INVALID_REG, size, INVALID_SREG); in GenArrayPut()
503 rl_src.high_reg, size, INVALID_SREG); in GenArrayPut()
[all …]
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| D | x86_lir.h | 132 … 0, 0, 0, 0, 0, 0, 1, rAX, INVALID_REG, INVALID_SREG, INVALID_SREG}
133 … 0, 0, 0, 0, 0, 0, 1, rAX, rDX, INVALID_SREG, INVALID_SREG}
134 … 0, 0, 1, 0, 0, 0, 1, fr0, INVALID_REG, INVALID_SREG, INVALID_SREG}
135 … 0, 0, 1, 0, 0, 0, 1, fr0, fr1, INVALID_SREG, INVALID_SREG}
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| D | utility_x86.cc | 448 r_dest, INVALID_REG, size, INVALID_SREG); in LoadBaseIndexed()
547 r_src, INVALID_REG, size, INVALID_SREG); in StoreBaseIndexed()
554 INVALID_SREG); in StoreBaseDisp()
560 r_src_lo, r_src_hi, kLong, INVALID_SREG); in StoreBaseDispWide()
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| /art/compiler/dex/quick/arm/ |
| D | arm_lir.h | 122 INVALID_SREG, INVALID_SREG}
124 INVALID_SREG, INVALID_SREG}
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| D | int_arm.cc | 812 LoadBaseDispWide(reg_ptr, data_offset, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); in GenArrayGet()
818 LoadBaseDisp(reg_ptr, data_offset, rl_result.low_reg, size, INVALID_SREG); in GenArrayGet()
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| D | utility_arm.cc | 803 -1, kWord, INVALID_SREG); in LoadBaseDispBody()
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| /art/compiler/dex/quick/ |
| D | gen_loadstore.cc | 80 INVALID_SREG); in LoadWordDisp()
132 reg_lo, reg_hi, INVALID_SREG); in LoadValueDirectWide()
167 DCHECK((live_sreg_ == INVALID_SREG) || in StoreValue()
234 DCHECK((live_sreg_ == INVALID_SREG) || in StoreValueWide()
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| D | ralloc_util.cc | 41 live_sreg_ = INVALID_SREG; in ResetRegPool()
57 regs[i].s_reg = INVALID_SREG; in CompilerInitPool()
108 live_sreg_ = INVALID_SREG; in ClobberSReg()
647 } else if (s_reg != INVALID_SREG) { in MarkLive()
727 if (my_sreg == INVALID_SREG) { in CheckCorePoolSanity()
728 DCHECK_EQ(partner_sreg, INVALID_SREG); in CheckCorePoolSanity()
865 DCHECK_NE(loc.s_reg_low, INVALID_SREG); in EvalLocWide()
866 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); in EvalLocWide()
902 DCHECK_NE(loc.s_reg_low, INVALID_SREG); in EvalLoc()
1156 return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; in GetSRegHi()
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| D | mir_to_lir-inl.h | 31 p->s_reg = INVALID_SREG; in ClobberBody()
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| D | mir_to_lir.cc | 734 live_sreg_ = INVALID_SREG; in MethodBlockCodeGen()
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| D | gen_common.cc | 476 rl_result.high_reg, INVALID_SREG); in GenSget()
673 LoadBaseDispWide(reg_ptr, 0, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); in GenIGet()
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| D | gen_invoke.cc | 1162 LoadBaseDispWide(rl_object.low_reg, 0, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); in GenInlinedUnsafeGet()
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| /art/compiler/dex/ |
| D | mir_graph.h | 164 #define INVALID_SREG (-1) macro
342 INVALID_REG, INVALID_REG, INVALID_SREG, INVALID_SREG};
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| D | vreg_analysis.cc | 366 INVALID_REG, INVALID_REG, INVALID_SREG,
367 INVALID_SREG};
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