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Searched refs:RA (Results 1 – 9 of 9) sorted by relevance

/art/runtime/arch/mips/
Dcontext_mips.cc36 gprs_[RA] = &ra_; in Reset()
39 ra_ = MipsContext::kBadGprBase + RA; in Reset()
Dregisters_mips.cc31 if (rhs >= ZERO && rhs <= RA) { in operator <<()
Dcontext_mips.h43 SetGPR(RA, new_pc); in SetPC()
Dregisters_mips.h61 RA = 31, // Return address. enumerator
/art/compiler/dex/quick/x86/
Dx86_lir.h250 opcode ## 8RR, opcode ## 8RM, opcode ## 8RA, opcode ## 8RT, \
253 opcode ## 16RR, opcode ## 16RM, opcode ## 16RA, opcode ## 16RT, \
257 opcode ## 32RR, opcode ## 32RM, opcode ## 32RA, opcode ## 32RT, \
318 opcode ## RR, opcode ## RM, opcode ## RA
Dassemble_x86.cc42 { kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES …
54 { kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODE…
70 { kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODE…
252 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x…
/art/compiler/jni/quick/mips/
Dcalling_convention_mips.cc140 1 << T7 | 1 << T8 | 1 << RA; in CoreSpillMask()
/art/compiler/utils/mips/
Dassembler_mips.cc352 EmitR(0, rs, static_cast<Register>(0), RA, 0, 0x09); in Jalr()
561 StoreToOffset(kStoreWord, RA, SP, stack_offset); in BuildFrame()
589 LoadFromOffset(kLoadWord, RA, SP, stack_offset); in RemoveFrame()
595 Jr(RA); in RemoveFrame()
/art/runtime/
Druntime.cc1229 (type == kSaveAll ? all_spills : 0) | (1 << art::mips::RA); in CreateCalleeSaveMethod()