Searched refs:def_mask (Results 1 – 11 of 11) sorted by relevance
25 ((use | def) & check->def_mask))110 uint64_t this_mem_mask = (this_lir->use_mask | this_lir->def_mask) & ENCODE_MEM; in ApplyLoadStoreElimination()120 uint64_t stop_def_reg_mask = this_lir->def_mask & ~ENCODE_MEM; in ApplyLoadStoreElimination()143 uint64_t check_mem_mask = (check_lir->use_mask | check_lir->def_mask) & ENCODE_MEM; in ApplyLoadStoreElimination()317 uint64_t stop_def_reg_mask = this_lir->def_mask & ~ENCODE_MEM; in ApplyLoadHoisting()332 uint64_t check_mem_mask = check_lir->def_mask & ENCODE_MEM; in ApplyLoadHoisting()410 if (prev_lir->def_mask == ENCODE_ALL) { in ApplyLoadHoisting()440 if (((cur_lir->use_mask & prev_lir->def_mask) && prev_is_load) || (slot < LD_LATENCY)) { in ApplyLoadHoisting()
56 insn->use_mask = insn->def_mask = ENCODE_ALL; in RawLIR()140 lir->use_mask = lir->def_mask = 0; in SetupResourceMasks()164 lir->def_mask = lir->use_mask = ENCODE_ALL; in SetupResourceMasks()169 SetupRegMask(&lir->def_mask, lir->operands[0]); in SetupResourceMasks()173 SetupRegMask(&lir->def_mask, lir->operands[1]); in SetupResourceMasks()178 lir->def_mask |= ENCODE_CCODE; in SetupResourceMasks()
48 inst->def_mask = ENCODE_ALL; in MarkSafepointPC()50 DCHECK_EQ(safepoint_pc->def_mask, ENCODE_ALL); in MarkSafepointPC()70 mask_ptr = &lir->def_mask; in SetMemRefType()196 if (lir->def_mask && (!lir->flags.is_nop || dump_nop)) { in DumpLIRInsn()197 DUMP_RESOURCE_MASK(DumpResourceMask(lir, lir->def_mask, "def")); in DumpLIRInsn()
749 head_lir->def_mask = ENCODE_ALL; in MethodBlockCodeGen()
814 ld->def_mask = ENCODE_ALL; in GenDalvikArgsRange()823 st->def_mask = ENCODE_ALL; in GenDalvikArgsRange()
127 uint64_t def_mask; // Resource mask for def. member
40 barrier->def_mask = -1; in GenBarrier()
129 lir->def_mask |= ENCODE_ARM_REG_SP; in SetupTargetResourceMasks()137 lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]); in SetupTargetResourceMasks()141 lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]); in SetupTargetResourceMasks()145 lir->def_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]); in SetupTargetResourceMasks()150 SetupRegMask(&lir->def_mask, lir->operands[1] + i); in SetupTargetResourceMasks()160 lir->def_mask = ENCODE_ALL; in SetupTargetResourceMasks()186 } else if ((opcode == kThumbPop) && (lir->def_mask & r8Mask)) { in SetupTargetResourceMasks()187 lir->def_mask &= ~r8Mask; in SetupTargetResourceMasks()188 lir->def_mask |= ENCODE_ARM_REG_PC; in SetupTargetResourceMasks()192 lir->def_mask |= ENCODE_ARM_REG_LR; in SetupTargetResourceMasks()
621 dmb->def_mask = ENCODE_ALL; in GenMemBarrier()
146 lir->def_mask |= ENCODE_X86_REG_SP; in SetupTargetResourceMasks()150 SetupRegMask(&lir->def_mask, rAX); in SetupTargetResourceMasks()154 SetupRegMask(&lir->def_mask, rDX); in SetupTargetResourceMasks()
130 lir->def_mask |= ENCODE_MIPS_REG_SP; in SetupTargetResourceMasks()138 lir->def_mask |= ENCODE_MIPS_REG_LR; in SetupTargetResourceMasks()