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Searched refs:inst (Results 1 – 24 of 24) sorted by relevance

/art/runtime/interpreter/
Dinterpreter.cc421 const Instruction* inst, JValue* result) NO_THREAD_SAFETY_ANALYSIS;
425 const Instruction* inst, JValue* result) { in DoInvoke() argument
427 uint32_t method_idx = (is_range) ? inst->VRegB_3rc() : inst->VRegB_35c(); in DoInvoke()
428 uint32_t vregC = (is_range) ? inst->VRegC_3rc() : inst->VRegC_35c(); in DoInvoke()
474 inst->GetArgs(arg); in DoInvoke()
528 const Instruction* inst, JValue* result)
533 const Instruction* inst, JValue* result) { in DoInvokeVirtualQuick() argument
534 uint32_t vregC = (is_range) ? inst->VRegC_3rc() : inst->VRegC_35c(); in DoInvokeVirtualQuick()
542 uint32_t vtable_idx = (is_range) ? inst->VRegB_3rc() : inst->VRegB_35c(); in DoInvokeVirtualQuick()
584 inst->GetArgs(arg); in DoInvokeVirtualQuick()
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/art/compiler/dex/
Ddex_to_dex_compiler.cc66 void CompileReturnVoid(Instruction* inst, uint32_t dex_pc);
71 Instruction* CompileCheckCast(Instruction* inst, uint32_t dex_pc);
79 void CompileInstanceFieldAccess(Instruction* inst, uint32_t dex_pc,
88 void CompileInvokeVirtual(Instruction* inst, uint32_t dex_pc,
103 Instruction* inst = const_cast<Instruction*>(Instruction::At(insns)); in Compile() local
106 inst = const_cast<Instruction*>(inst->Next()), dex_pc = inst->GetDexPc(insns)) { in Compile()
107 switch (inst->Opcode()) { in Compile()
109 CompileReturnVoid(inst, dex_pc); in Compile()
113 inst = CompileCheckCast(inst, dex_pc); in Compile()
117 CompileInstanceFieldAccess(inst, dex_pc, Instruction::IGET_QUICK, false); in Compile()
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/art/compiler/sea_ir/ir/
Dinstruction_nodes.h111 explicit ConstInstructionNode(const art::Instruction* inst): in ConstInstructionNode() argument
112 InstructionNode(inst) { } in ConstInstructionNode()
126 explicit UnnamedConstInstructionNode(const art::Instruction* inst, int32_t value): in UnnamedConstInstructionNode() argument
127 ConstInstructionNode(inst), value_(value) { } in UnnamedConstInstructionNode()
148 explicit ReturnInstructionNode(const art::Instruction* inst): InstructionNode(inst) { } in ReturnInstructionNode() argument
157 explicit IfNeInstructionNode(const art::Instruction* inst): InstructionNode(inst) { in IfNeInstructionNode() argument
158 DCHECK(InstructionTools::IsDefinition(inst) == false); in IfNeInstructionNode()
170 explicit MoveResultInstructionNode(const art::Instruction* inst): InstructionNode(inst) { } in MoveResultInstructionNode() argument
184 explicit InvokeStaticInstructionNode(const art::Instruction* inst): InstructionNode(inst), in InvokeStaticInstructionNode() argument
185 method_index_(inst->VRegB_35c()) { } in InvokeStaticInstructionNode()
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Dsea.cc208 const art::Instruction* inst = art::Instruction::At(&code[i]); in BuildMethodSeaGraph() local
209 if (inst->IsBranch() || inst->IsUnconditional()) { in BuildMethodSeaGraph()
210 int32_t offset = inst->GetTargetOffset(); in BuildMethodSeaGraph()
215 if (inst->CanFlowThrough() in BuildMethodSeaGraph()
216 && (target_regions.end() == target_regions.find(&code[i + inst->SizeInCodeUnits()]))) { in BuildMethodSeaGraph()
219 std::pair<const uint16_t*, Region*>(&code[i + inst->SizeInCodeUnits()], region)); in BuildMethodSeaGraph()
222 i += inst->SizeInCodeUnits(); in BuildMethodSeaGraph()
235 const art::Instruction* inst = art::Instruction::At(&code[i]); in BuildMethodSeaGraph() local
237 sea_ir::InstructionNode::Create(inst); in BuildMethodSeaGraph()
243 if (inst->IsBranch() || inst->IsUnconditional()) { in BuildMethodSeaGraph()
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/art/runtime/verifier/
Dmethod_verifier.cc361 const Instruction* inst = Instruction::At(code_item_->insns_ + dex_pc); in FindAccessedFieldAtDexPc() local
362 return GetQuickFieldAccess(inst, register_line); in FindAccessedFieldAtDexPc()
389 const Instruction* inst = Instruction::At(code_item_->insns_ + dex_pc); in FindInvokedMethodAtDexPc() local
390 const bool is_range = (inst->Opcode() == Instruction::INVOKE_VIRTUAL_RANGE_QUICK); in FindInvokedMethodAtDexPc()
391 return GetQuickInvokedMethod(inst, register_line, is_range); in FindInvokedMethodAtDexPc()
491 const Instruction* inst = Instruction::At(insns); in ComputeWidthsAndCountOps() local
497 Instruction::Code opcode = inst->Opcode(); in ComputeWidthsAndCountOps()
504 } else if ((inst->Opcode() == Instruction::INVOKE_VIRTUAL) || in ComputeWidthsAndCountOps()
505 (inst->Opcode() == Instruction::INVOKE_VIRTUAL_RANGE) || in ComputeWidthsAndCountOps()
506 (inst->Opcode() == Instruction::INVOKE_INTERFACE) || in ComputeWidthsAndCountOps()
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Dregister_line.cc91 const RegType& RegisterLine::GetInvocationThis(const Instruction* inst, bool is_range) { in GetInvocationThis() argument
92 const size_t args_count = is_range ? inst->VRegA_3rc() : inst->VRegA_35c(); in GetInvocationThis()
98 const uint32_t this_reg = (is_range) ? inst->VRegC_3rc() : inst->VRegC_35c(); in GetInvocationThis()
282 void RegisterLine::CheckUnaryOp(const Instruction* inst, in CheckUnaryOp() argument
285 if (VerifyRegisterType(inst->VRegB_12x(), src_type)) { in CheckUnaryOp()
286 SetRegisterType(inst->VRegA_12x(), dst_type); in CheckUnaryOp()
290 void RegisterLine::CheckUnaryOpWide(const Instruction* inst, in CheckUnaryOpWide() argument
293 if (VerifyRegisterTypeWide(inst->VRegB_12x(), src_type1, src_type2)) { in CheckUnaryOpWide()
294 SetRegisterTypeWide(inst->VRegA_12x(), dst_type1, dst_type2); in CheckUnaryOpWide()
298 void RegisterLine::CheckUnaryOpToWide(const Instruction* inst, in CheckUnaryOpToWide() argument
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Dregister_line.h179 const RegType& GetInvocationThis(const Instruction* inst, bool is_range)
186 void CheckUnaryOp(const Instruction* inst, const RegType& dst_type,
190 void CheckUnaryOpWide(const Instruction* inst,
195 void CheckUnaryOpToWide(const Instruction* inst,
200 void CheckUnaryOpFromWide(const Instruction* inst,
210 void CheckBinaryOp(const Instruction* inst,
215 void CheckBinaryOpWide(const Instruction* inst,
221 void CheckBinaryOpWideShift(const Instruction* inst,
230 void CheckBinaryOp2addr(const Instruction* inst,
236 void CheckBinaryOp2addrWide(const Instruction* inst,
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Dmethod_verifier.h350 bool VerifyInstruction(const Instruction* inst, uint32_t code_offset);
481 void VerifyNewArray(const Instruction* inst, bool is_filled, bool is_range)
492 void VerifyAGet(const Instruction* inst, const RegType& insn_type,
496 void VerifyAPut(const Instruction* inst, const RegType& insn_type,
507 void VerifyISGet(const Instruction* inst, const RegType& insn_type,
512 void VerifyISPut(const Instruction* inst, const RegType& insn_type,
518 mirror::ArtField* GetQuickFieldAccess(const Instruction* inst, RegisterLine* reg_line)
522 void VerifyIGetQuick(const Instruction* inst, const RegType& insn_type,
527 void VerifyIPutQuick(const Instruction* inst, const RegType& insn_type,
574 mirror::ArtMethod* VerifyInvocationArgs(const Instruction* inst,
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/art/runtime/
Ddex_instruction_visitor.h33 const Instruction* inst = Instruction::At(&code[i]); in Visit() local
34 switch (inst->Opcode()) { in Visit()
37 derived->Do_ ## cname(inst); \ in Visit()
47 i += inst->SizeInCodeUnits(); in Visit()
54 void Do_ ## cname(const Instruction* inst) { \
56 derived->Do_Default(inst); \
Ddex_instruction.h445 explicit DecodedInstruction(const Instruction* inst) { in DecodedInstruction()
446 inst->Decode(vA, vB, vB_wide, vC, arg); in DecodedInstruction()
447 opcode = inst->Opcode(); in DecodedInstruction()
Dthread.cc1814 const Instruction* inst = Instruction::At(code_item->insns_ + dex_pc); in HandleDeoptimization() local
1815 uint32_t new_dex_pc = dex_pc + inst->SizeInCodeUnits(); in HandleDeoptimization()
/art/test/003-omnibus-opcodes/src/
DMethodCall.java54 MethodCall inst = new MethodCall(); in run() local
56 MethodCallBase base = inst; in run()
58 inst.tryThing(); in run()
60 inst = null; in run()
62 inst.directly(); in run()
/art/test/043-privates/src/
DMain.java45 PrivatePackage inst = new PrivatePackageSub(); in stretchTest() local
46 System.out.println("PrivatePackage --> " + inst.getStr()); in stretchTest()
47 System.out.println("PrivatePackage --> " + inst.privGetStr()); in stretchTest()
/art/compiler/llvm/
Dir_builder.h80 ::llvm::LoadInst* inst = LLVMIRBuilder::CreateLoad(ptr); in CreateLoad()
81 inst->setMetadata(::llvm::LLVMContext::MD_tbaa, tbaa_info); in CreateLoad()
82 return inst; in CreateLoad()
86 ::llvm::StoreInst* inst = LLVMIRBuilder::CreateStore(val, ptr); in CreateStore()
87 inst->setMetadata(::llvm::LLVMContext::MD_tbaa, tbaa_info); in CreateStore()
88 return inst; in CreateStore()
94 ::llvm::AtomicCmpXchgInst* inst = in CreateAtomicCmpXchgInst()
96 inst->setMetadata(::llvm::LLVMContext::MD_tbaa, tbaa_info); in CreateAtomicCmpXchgInst()
97 return inst; in CreateAtomicCmpXchgInst()
175 void SetTBAA(::llvm::Instruction* inst, TBAASpecialType special_ty) { in SetTBAA() argument
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Dgbc_expander.cc167 llvm::Value* ExpandToRuntime(RuntimeId rt, llvm::CallInst& inst);
645 llvm::Value* GBCExpanderPass::ExpandToRuntime(RuntimeId rt, llvm::CallInst& inst) { in ExpandToRuntime() argument
649 unsigned num_args = inst.getNumArgOperands(); in ExpandToRuntime()
656 args.push_back(inst.getArgOperand(i)); in ExpandToRuntime()
/art/compiler/sea_ir/types/
Dtype_inference.h63 FunctionTypeInfo(const SeaGraph* graph, InstructionNode* inst,
Dtype_inference.cc47 FunctionTypeInfo::FunctionTypeInfo(const SeaGraph* graph, InstructionNode* inst, in FunctionTypeInfo() argument
49 dex_method_idx_(inst->GetInstruction()->VRegB_35c()), type_cache_(types), in FunctionTypeInfo()
/art/compiler/utils/mips/
Dassembler_mips.cc136 int32_t MipsAssembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) { in EncodeBranchOffset() argument
144 return (inst & ~kJumpOffsetMask) | offset; in EncodeBranchOffset()
147 return (inst & ~kBranchOffsetMask) | offset; in EncodeBranchOffset()
151 int MipsAssembler::DecodeBranchOffset(int32_t inst, bool is_jump) { in DecodeBranchOffset() argument
154 return (((inst & kJumpOffsetMask) << 6) >> 4); in DecodeBranchOffset()
156 return (((inst & kBranchOffsetMask) << 16) >> 14); in DecodeBranchOffset()
Dassembler_mips.h487 int32_t EncodeBranchOffset(int offset, int32_t inst, bool is_jump);
488 int DecodeBranchOffset(int32_t inst, bool is_jump);
/art/compiler/utils/arm/
Dassembler_arm.h633 static int32_t EncodeBranchOffset(int offset, int32_t inst);
634 static int DecodeBranchOffset(int32_t inst);
635 int32_t EncodeTstOffset(int offset, int32_t inst);
636 int DecodeTstOffset(int32_t inst);
Dassembler_arm.cc1106 int32_t ArmAssembler::EncodeBranchOffset(int offset, int32_t inst) { in EncodeBranchOffset() argument
1115 return (inst & ~kBranchOffsetMask) | offset; in EncodeBranchOffset()
1119 int ArmAssembler::DecodeBranchOffset(int32_t inst) { in DecodeBranchOffset() argument
1121 return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8); in DecodeBranchOffset()
/art/compiler/dex/portable/
Dmir_to_gbc.cc74 ::llvm::Instruction* inst = ::llvm::dyn_cast< ::llvm::Instruction>(placeholder); in DefineValueOnly()
75 DCHECK(inst != NULL); in DefineValueOnly()
76 inst->eraseFromParent(); in DefineValueOnly()
1520 ::llvm::Instruction* inst = irb_->CreateCall(intr); in SetMethodInfo()
1528 inst->setMetadata("RegInfo", reg_info_node); in SetMethodInfo()
1932 ::llvm::Instruction* inst = ::llvm::dyn_cast< ::llvm::Instruction>(it++); in MethodMIR2Bitcode()
1933 DCHECK(inst != NULL); in MethodMIR2Bitcode()
1934 ::llvm::Value* val = ::llvm::dyn_cast< ::llvm::Value>(inst); in MethodMIR2Bitcode()
1937 inst->eraseFromParent(); in MethodMIR2Bitcode()
/art/compiler/dex/quick/
Dcodegen_util.cc47 void Mir2Lir::MarkSafepointPC(LIR* inst) { in MarkSafepointPC() argument
48 inst->def_mask = ENCODE_ALL; in MarkSafepointPC()
Dmir_to_lir.h252 void MarkSafepointPC(LIR* inst);