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Searched refs:mir (Results 1 – 25 of 28) sorted by relevance

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/art/compiler/dex/
Dlocal_value_numbering.cc22 uint16_t LocalValueNumbering::GetValueNumber(MIR* mir) { in GetValueNumber() argument
24 uint16_t opcode = mir->dalvikInsn.opcode; in GetValueNumber()
83 uint16_t res = GetOperandValue(mir->ssa_rep->defs[0]); in GetValueNumber()
84 SetOperandValue(mir->ssa_rep->defs[0], res); in GetValueNumber()
89 uint16_t res = GetOperandValueWide(mir->ssa_rep->defs[0]); in GetValueNumber()
90 SetOperandValueWide(mir->ssa_rep->defs[0], res); in GetValueNumber()
109 uint16_t res = GetOperandValue(mir->ssa_rep->uses[0]); in GetValueNumber()
110 SetOperandValue(mir->ssa_rep->defs[0], res); in GetValueNumber()
118 uint16_t res = GetOperandValueWide(mir->ssa_rep->uses[0]); in GetValueNumber()
119 SetOperandValueWide(mir->ssa_rep->defs[0], res); in GetValueNumber()
[all …]
Dmir_optimization.cc40 MIR* mir; in DoConstantPropogation() local
42 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { in DoConstantPropogation()
43 int df_attributes = oat_data_flow_attributes_[mir->dalvikInsn.opcode]; in DoConstantPropogation()
45 DecodedInstruction *d_insn = &mir->dalvikInsn; in DoConstantPropogation()
57 SetConstant(mir->ssa_rep->defs[0], vB); in DoConstantPropogation()
60 SetConstant(mir->ssa_rep->defs[0], vB << 16); in DoConstantPropogation()
64 SetConstantWide(mir->ssa_rep->defs[0], static_cast<int64_t>(vB)); in DoConstantPropogation()
67 SetConstantWide(mir->ssa_rep->defs[0], d_insn->vB_wide); in DoConstantPropogation()
70 SetConstantWide(mir->ssa_rep->defs[0], static_cast<int64_t>(vB) << 48); in DoConstantPropogation()
80 for (i = 0; i < mir->ssa_rep->num_uses; i++) { in DoConstantPropogation()
[all …]
Dmir_dataflow.cc869 MIR* mir; in FindLocalLiveIn() local
881 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { in FindLocalLiveIn()
882 int df_attributes = oat_data_flow_attributes_[mir->dalvikInsn.opcode]; in FindLocalLiveIn()
883 DecodedInstruction *d_insn = &mir->dalvikInsn; in FindLocalLiveIn()
951 void MIRGraph::DataFlowSSAFormat35C(MIR* mir) { in DataFlowSSAFormat35C() argument
952 DecodedInstruction *d_insn = &mir->dalvikInsn; in DataFlowSSAFormat35C()
956 mir->ssa_rep->num_uses = num_uses; in DataFlowSSAFormat35C()
957 mir->ssa_rep->uses = static_cast<int*>(arena_->Alloc(sizeof(int) * num_uses, in DataFlowSSAFormat35C()
960 mir->ssa_rep->fp_use = static_cast<bool*>(arena_->Alloc(sizeof(bool) * num_uses, in DataFlowSSAFormat35C()
964 HandleSSAUse(mir->ssa_rep->uses, d_insn->arg[i], i); in DataFlowSSAFormat35C()
[all …]
Dmir_graph.h499 RegLocation GetRawSrc(MIR* mir, int num) { in GetRawSrc() argument
500 DCHECK(num < mir->ssa_rep->num_uses); in GetRawSrc()
501 RegLocation res = reg_location_[mir->ssa_rep->uses[num]]; in GetRawSrc()
505 RegLocation GetRawDest(MIR* mir) { in GetRawDest() argument
506 DCHECK_GT(mir->ssa_rep->num_defs, 0); in GetRawDest()
507 RegLocation res = reg_location_[mir->ssa_rep->defs[0]]; in GetRawDest()
511 RegLocation GetDest(MIR* mir) { in GetDest() argument
512 RegLocation res = GetRawDest(mir); in GetDest()
517 RegLocation GetSrc(MIR* mir, int num) { in GetSrc() argument
518 RegLocation res = GetRawSrc(mir, num); in GetSrc()
[all …]
Dmir_graph.cc739 const MIR *mir; in DumpCFG() local
742 for (mir = bb->first_mir_insn; mir; mir = mir->next) { in DumpCFG()
743 int opcode = mir->dalvikInsn.opcode; in DumpCFG()
744 fprintf(file, " {%04x %s %s %s\\l}%s\\\n", mir->offset, in DumpCFG()
745 mir->ssa_rep ? GetDalvikDisassembly(mir) : in DumpCFG()
746 (opcode < kMirOpFirst) ? Instruction::Name(mir->dalvikInsn.opcode) : in DumpCFG()
748 … (mir->optimization_flags & MIR_IGNORE_RANGE_CHECK) != 0 ? " no_rangecheck" : " ", in DumpCFG()
749 (mir->optimization_flags & MIR_IGNORE_NULL_CHECK) != 0 ? " no_nullcheck" : " ", in DumpCFG()
750 mir->next ? " | " : " "); in DumpCFG()
838 void MIRGraph::AppendMIR(BasicBlock* bb, MIR* mir) { in AppendMIR() argument
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Dvreg_analysis.cc76 MIR *mir; in InferTypeAndSize() local
83 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { in InferTypeAndSize()
84 SSARepresentation *ssa_rep = mir->ssa_rep; in InferTypeAndSize()
86 int attrs = oat_data_flow_attributes_[mir->dalvikInsn.opcode]; in InferTypeAndSize()
160 if ((mir->dalvikInsn.opcode == Instruction::RETURN) || in InferTypeAndSize()
161 (mir->dalvikInsn.opcode == Instruction::RETURN_WIDE) || in InferTypeAndSize()
162 (mir->dalvikInsn.opcode == Instruction::RETURN_OBJECT)) { in InferTypeAndSize()
192 Instruction::Code opcode = mir->dalvikInsn.opcode; in InferTypeAndSize()
194 ? 0 : Instruction::FlagsOf(mir->dalvikInsn.opcode); in InferTypeAndSize()
198 int target_idx = mir->dalvikInsn.vB; in InferTypeAndSize()
[all …]
Dssa_transformation.cc582 MIR *mir; in InsertPhiNodeOperands() local
587 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { in InsertPhiNodeOperands()
588 if (mir->dalvikInsn.opcode != static_cast<Instruction::Code>(kMirOpPhi)) in InsertPhiNodeOperands()
590 int ssa_reg = mir->ssa_rep->defs[0]; in InsertPhiNodeOperands()
611 mir->ssa_rep->num_uses = num_uses; in InsertPhiNodeOperands()
612 mir->ssa_rep->uses = in InsertPhiNodeOperands()
614 mir->ssa_rep->fp_use = in InsertPhiNodeOperands()
619 mir->dalvikInsn.vB = reinterpret_cast<uintptr_t>(incoming); in InsertPhiNodeOperands()
622 int *use_ptr = mir->ssa_rep->uses; in InsertPhiNodeOperands()
Dmir_analysis.cc893 for (MIR* mir = tbb->first_mir_insn; mir != NULL; mir = mir->next) { in AnalyzeBlock() local
894 if (static_cast<uint32_t>(mir->dalvikInsn.opcode) >= kMirOpFirst) { in AnalyzeBlock()
898 uint32_t flags = analysis_attributes_[mir->dalvikInsn.opcode]; in AnalyzeBlock()
Dlocal_value_numbering.h129 uint16_t GetValueNumber(MIR* mir);
/art/compiler/dex/quick/arm/
Dcall_arm.cc82 void ArmMir2Lir::LockLiveArgs(MIR* mir) { in LockLiveArgs() argument
85 for (int i = 0; i < mir->ssa_rep->num_uses; i++) { in LockLiveArgs()
86 int v_reg = mir_graph_->SRegToVReg(mir->ssa_rep->uses[i]); in LockLiveArgs()
96 MIR* ArmMir2Lir::GetNextMir(BasicBlock** p_bb, MIR* mir) { in GetNextMir() argument
98 MIR* orig_mir = mir; in GetNextMir()
100 if (mir != NULL) { in GetNextMir()
101 mir = mir->next; in GetNextMir()
103 if (mir != NULL) { in GetNextMir()
104 return mir; in GetNextMir()
109 mir = bb->first_mir_insn; in GetNextMir()
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Dcodegen_arm.h122 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
123 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
124 void GenSelect(BasicBlock* bb, MIR* mir);
133 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
134 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
135 void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
167 void GenPrintLabel(MIR* mir);
184 void LockLiveArgs(MIR* mir);
185 MIR* GetNextMir(BasicBlock** p_bb, MIR* mir);
186 MIR* SpecialIGet(BasicBlock** bb, MIR* mir, OpSize size, bool long_or_double, bool is_object);
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Dint_arm.cc179 void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect() argument
181 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); in GenSelect()
183 int dest_sreg = mir->ssa_rep->defs[0]; in GenSelect()
187 LOG(INFO) << "at dex offset 0x" << std::hex << mir->offset; in GenSelect()
189 LOG(INFO) << "num uses = " << mir->ssa_rep->num_uses; in GenSelect()
190 if (mir->ssa_rep->num_uses == 1) { in GenSelect()
191 LOG(INFO) << "CONST case, vals = " << mir->dalvikInsn.vB << ", " << mir->dalvikInsn.vC; in GenSelect()
193 LOG(INFO) << "MOVE case, operands = " << mir->ssa_rep->uses[1] << ", " in GenSelect()
194 << mir->ssa_rep->uses[2]; in GenSelect()
199 RegLocation rl_dest = mir_graph_->GetDest(mir); in GenSelect()
[all …]
Dfp_arm.cc177 void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch() argument
183 rl_src1 = mir_graph_->GetSrcWide(mir, 0); in GenFusedFPCmpBranch()
184 rl_src2 = mir_graph_->GetSrcWide(mir, 2); in GenFusedFPCmpBranch()
190 rl_src1 = mir_graph_->GetSrc(mir, 0); in GenFusedFPCmpBranch()
191 rl_src2 = mir_graph_->GetSrc(mir, 1); in GenFusedFPCmpBranch()
197 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]); in GenFusedFPCmpBranch()
/art/compiler/dex/quick/
Dmir_to_lir.cc29 void Mir2Lir::CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list) { in CompileDalvikInstruction() argument
33 Instruction::Code opcode = mir->dalvikInsn.opcode; in CompileDalvikInstruction()
34 int opt_flags = mir->optimization_flags; in CompileDalvikInstruction()
35 uint32_t vB = mir->dalvikInsn.vB; in CompileDalvikInstruction()
36 uint32_t vC = mir->dalvikInsn.vC; in CompileDalvikInstruction()
45 rl_src[next_loc++] = mir_graph_->GetSrcWide(mir, next_sreg); in CompileDalvikInstruction()
48 rl_src[next_loc++] = mir_graph_->GetSrc(mir, next_sreg); in CompileDalvikInstruction()
54 rl_src[next_loc++] = mir_graph_->GetSrcWide(mir, next_sreg); in CompileDalvikInstruction()
57 rl_src[next_loc++] = mir_graph_->GetSrc(mir, next_sreg); in CompileDalvikInstruction()
63 rl_src[next_loc++] = mir_graph_->GetSrcWide(mir, next_sreg); in CompileDalvikInstruction()
[all …]
Dmir_to_lir.h310 int oatSSASrc(MIR* mir, int num);
519 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list);
520 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir);
626 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
628 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0;
629 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0;
639 virtual void GenPackedSwitch(MIR* mir, uint32_t table_offset,
641 virtual void GenSparseSwitch(MIR* mir, uint32_t table_offset,
643 virtual void GenSpecialCase(BasicBlock* bb, MIR* mir,
/art/test/040-miranda/src/
DMain.java24 MirandaClass mir = new MirandaClass(); in main() local
26 System.out.println(" inInterface: " + mir.inInterface()); in main()
27 System.out.println(" inInterface2: " + mir.inInterface2()); in main()
28 System.out.println(" inAbstract: " + mir.inAbstract()); in main()
31 MirandaAbstract mira = mir; in main()
/art/compiler/dex/portable/
Dmir_to_gbc.cc312 void MirConverter::ConvertCompareAndBranch(BasicBlock* bb, MIR* mir, in ConvertCompareAndBranch() argument
314 if (bb->taken->start_offset <= mir->offset) { in ConvertCompareAndBranch()
328 MIR* mir, ConditionCode cc, RegLocation rl_src1) { in ConvertCompareZeroAndBranch() argument
329 if (bb->taken->start_offset <= mir->offset) { in ConvertCompareZeroAndBranch()
450 void MirConverter::ConvertInvoke(BasicBlock* bb, MIR* mir, in ConvertInvoke() argument
452 CallInfo* info = mir_graph_->NewMemCallInfo(bb, mir, invoke_type, is_range); in ConvertInvoke()
686 bool MirConverter::ConvertMIRNode(MIR* mir, BasicBlock* bb, in ConvertMIRNode() argument
691 Instruction::Code opcode = mir->dalvikInsn.opcode; in ConvertMIRNode()
693 uint32_t vB = mir->dalvikInsn.vB; in ConvertMIRNode()
694 uint32_t vC = mir->dalvikInsn.vC; in ConvertMIRNode()
[all …]
Dmir_to_gbc.h110 void ConvertCompareAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
112 void ConvertCompareZeroAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
128 void ConvertInvoke(BasicBlock* bb, MIR* mir, InvokeType invoke_type,
161 bool ConvertMIRNode(MIR* mir, BasicBlock* bb, ::llvm::BasicBlock* llvm_bb);
165 void ConvertExtendedMIR(BasicBlock* bb, MIR* mir, ::llvm::BasicBlock* llvm_bb);
/art/compiler/dex/quick/mips/
Dcodegen_mips.h123 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
124 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
125 void GenSelect(BasicBlock* bb, MIR* mir);
134 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
135 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
136 void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
Dcall_mips.cc26 void MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, in GenSpecialCase() argument
62 void MipsMir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset, in GenSparseSwitch() argument
141 void MipsMir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset, in GenPackedSwitch() argument
Dfp_mips.cc215 void MipsMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, in GenFusedFPCmpBranch() argument
/art/compiler/dex/quick/x86/
Dcodegen_x86.h123 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
124 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
125 void GenSelect(BasicBlock* bb, MIR* mir);
134 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
135 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
136 void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
Dfp_x86.cc285 void X86Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch() argument
293 rl_src1 = mir_graph_->GetSrcWide(mir, 0); in GenFusedFPCmpBranch()
294 rl_src2 = mir_graph_->GetSrcWide(mir, 2); in GenFusedFPCmpBranch()
300 rl_src1 = mir_graph_->GetSrc(mir, 0); in GenFusedFPCmpBranch()
301 rl_src2 = mir_graph_->GetSrc(mir, 1); in GenFusedFPCmpBranch()
306 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]); in GenFusedFPCmpBranch()
Dcall_x86.cc25 void X86Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, in GenSpecialCase() argument
34 void X86Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset, in GenSparseSwitch() argument
69 void X86Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset, in GenPackedSwitch() argument
Dint_x86.cc164 void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect() argument
168 void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { in GenFusedLongCmpBranch() argument
170 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); in GenFusedLongCmpBranch()
171 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); in GenFusedLongCmpBranch()
176 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]); in GenFusedLongCmpBranch()

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