| /dalvik/vm/compiler/codegen/mips/ |
| D | CodegenFactory.cpp | 48 int reg1) in loadValueDirect() argument
52 genRegCopy(cUnit, reg1, rlSrc.lowReg); in loadValueDirect()
54 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1); in loadValueDirect()
58 reg1); in loadValueDirect()
68 int reg1) in loadValueDirectFixed() argument
70 dvmCompilerClobber(cUnit, reg1); in loadValueDirectFixed()
71 dvmCompilerMarkInUse(cUnit, reg1); in loadValueDirectFixed()
72 loadValueDirect(cUnit, rlSrc, reg1); in loadValueDirectFixed()
284 int reg1, int reg2, int dOffset, in genRegRegCheck() argument
290 res = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2); in genRegRegCheck()
[all …]
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| D | RallocUtil.cpp | 107 static void flushRegWide(CompilationUnit *cUnit, int reg1, int reg2) in flushRegWide() argument
109 RegisterInfo *info1 = getRegInfo(cUnit, reg1); in flushRegWide()
1017 int reg1, int reg2) in dvmCompilerFlushRegWideForV5TEVFP() argument
1019 flushRegWide(cUnit, reg1, reg2); in dvmCompilerFlushRegWideForV5TEVFP()
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| D | CodegenDriver.cpp | 2680 int reg1 = rlSrc1.lowReg; in handleFmt22t() local
2694 test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2); in handleFmt22t()
2695 reg1 = tReg; in handleFmt22t()
2701 test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1); in handleFmt22t()
2702 reg1 = tReg; in handleFmt22t()
2708 test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1); in handleFmt22t()
2709 reg1 = tReg; in handleFmt22t()
2715 test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2); in handleFmt22t()
2716 reg1 = tReg; in handleFmt22t()
2725 genConditionalBranchMips(cUnit, opc, reg1, reg2, &labelList[bb->taken->id]); in handleFmt22t()
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| /dalvik/vm/compiler/codegen/ |
| D | CodegenFactory.cpp | 54 int reg1) in loadValueDirect() argument
58 genRegCopy(cUnit, reg1, rlSrc.lowReg); in loadValueDirect()
60 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1); in loadValueDirect()
64 reg1); in loadValueDirect()
74 int reg1) in loadValueDirectFixed() argument
76 dvmCompilerClobber(cUnit, reg1); in loadValueDirectFixed()
77 dvmCompilerMarkInUse(cUnit, reg1); in loadValueDirectFixed()
78 loadValueDirect(cUnit, rlSrc, reg1); in loadValueDirectFixed()
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| D | Ralloc.h | 202 extern void dvmCompilerFlushRegWide(CompilationUnit *cUnit, int reg1, int reg2);
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| D | RallocUtil.cpp | 105 void dvmCompilerFlushRegWide(CompilationUnit *cUnit, int reg1, int reg2) in dvmCompilerFlushRegWide() argument
107 RegisterInfo *info1 = getRegInfo(cUnit, reg1); in dvmCompilerFlushRegWide()
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| /dalvik/vm/compiler/codegen/arm/ |
| D | ArchFactory.cpp | 74 int reg1, int reg2, int dOffset, in genRegRegCheck() argument
78 res = opRegReg(cUnit, kOpCmp, reg1, reg2); in genRegRegCheck()
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| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| D | Gen.cpp | 290 int reg1 = loadValue(cUnit, rlSrc2, kCoreReg).lowReg; in genInlinedMinMaxInt() local
293 newLIR3(cUnit, kMipsSlt, tReg, reg0, reg1); in genInlinedMinMaxInt()
296 newLIR3(cUnit, kMipsSlt, tReg, reg1, reg0); in genInlinedMinMaxInt()
298 newLIR3(cUnit, kMipsMovz, reg0, reg1, tReg); in genInlinedMinMaxInt()
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| D | Factory.cpp | 41 int reg1, int reg2, int dOffset,
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| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| D | Gen.cpp | 255 int reg1 = loadValue(cUnit, rlSrc2, kCoreReg).lowReg; in genInlinedMinMaxInt() local
256 newLIR2(cUnit, kThumbCmpRR, reg0, reg1); in genInlinedMinMaxInt()
259 newLIR2(cUnit, kThumbMovRR, reg0, reg1); in genInlinedMinMaxInt()
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| D | Factory.cpp | 36 int reg1, int reg2, int dOffset,
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| /dalvik/vm/compiler/codegen/x86/ |
| D | Lower.h | 645 void compare_reg_reg(int reg1, bool isPhysical1,
647 void compare_reg_reg_16(int reg1, bool isPhysical1,
651 void compare_ss_reg_with_reg(LowOp* op, int reg1, bool isPhysical1,
655 void compare_sd_reg_with_reg(LowOp* op, int reg1, bool isPhysical1,
661 void conditional_move_reg_to_reg(OpndSize size, ConditionCode cc, int reg1, bool isPhysical1, int r…
700 int reg1, bool isPhysical1,
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| D | LowerHelper.cpp | 1131 void compare_reg_reg(int reg1, bool isPhysical1, in compare_reg_reg() argument
1134 …dump_reg_reg(m, ATOM_NORMAL, OpndSize_32, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_gp); in compare_reg_reg()
1136 void compare_reg_reg_16(int reg1, bool isPhysical1, in compare_reg_reg_16() argument
1139 …dump_reg_reg(m, ATOM_NORMAL, OpndSize_16, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_gp); in compare_reg_reg_16()
1154 void compare_ss_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, in compare_ss_reg_with_reg() argument
1157 …dump_reg_reg(m, ATOM_NORMAL, OpndSize_32, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_xm… in compare_ss_reg_with_reg()
1171 void compare_sd_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, in compare_sd_reg_with_reg() argument
1174 …dump_reg_reg(m, ATOM_NORMAL, OpndSize_64, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_xmm… in compare_sd_reg_with_reg()
1370 int reg1, bool isPhysical1, in alu_binary_reg_reg() argument
1377 …dump_reg_reg(m, ATOM_NORMAL_ALU, size, reg1, isPhysical1, reg2, isPhysical2, getTypeFromIntSize(si… in alu_binary_reg_reg()
[all …]
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| /dalvik/vm/compiler/codegen/mips/FP/ |
| D | MipsFP.cpp | 23 int reg1, int reg2);
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| /dalvik/vm/analysis/ |
| D | CodeVerify.cpp | 2084 static bool upcastBooleanOp(RegisterLine* registerLine, u4 reg1, u4 reg2) in upcastBooleanOp() argument
2088 type1 = getRegisterType(registerLine, reg1); in upcastBooleanOp()
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