| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 253 case ISD::ADDE: { in selectNode()
256 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode()
261 if (Opcode == ISD::ADDE) { in selectNode()
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| D | MipsSEISelDAGToDAG.cpp | 221 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
336 case ISD::ADDE: { in selectNode()
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| D | MipsSEISelLowering.cpp | 114 setTargetDAGCombine(ISD::ADDE); in MipsSETargetLowering()
497 case ISD::ADDE: in PerformDAGCombine()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 204 ADDE, SUBE, enumerator
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| D | SelectionDAG.h | 944 case ISD::ADDE: return true;
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| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 102 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
196 setOperationAction(ISD::ADDE, MVT::Other, Expand); in InitAMDILLowering()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
213 setOperationAction(ISD::ADDE, MVT::Other, Expand); in InitAMDILLowering()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
213 setOperationAction(ISD::ADDE, MVT::Other, Expand); in InitAMDILLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1386 setOperationAction(ISD::ADDE, MVT::i8, Expand); in HexagonTargetLowering()
1387 setOperationAction(ISD::ADDE, MVT::i16, Expand); in HexagonTargetLowering()
1388 setOperationAction(ISD::ADDE, MVT::i32, Expand); in HexagonTargetLowering()
1389 setOperationAction(ISD::ADDE, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 81 ADDE, // Add using carry enumerator
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| D | ARMISelLowering.cpp | 668 setOperationAction(ISD::ADDE, MVT::i32, Custom); in ARMTargetLowering()
996 case ARMISD::ADDE: return "ARMISD::ADDE"; in getTargetNodeName()
5760 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
5902 case ISD::ADDE: in LowerOperation()
8046 if (AddeNode->getOpcode() != ISD::ADDE) in AddCombineTo64bitMLAL()
10415 case ARMISD::ADDE: in computeMaskedBitsForTargetNode()
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| D | ARMInstrInfo.td | 154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
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| /external/qemu/tcg/ppc/ |
| D | tcg-target.c | 346 #define ADDE XO31(138) macro
1617 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); in tcg_out_op()
1622 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); in tcg_out_op()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 197 case ISD::ADDE: return "adde"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1160 case ISD::ADDE: in ExpandIntegerResult()
1298 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); in ExpandShiftByConstant()
1549 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1598 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
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| D | SelectionDAG.cpp | 2026 case ISD::ADDE: { in ComputeMaskedBits()
3201 case ISD::ADDE: in getNode()
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| D | DAGCombiner.cpp | 1112 case ISD::ADDE: return visitADDE(N); in visit()
1603 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), in visitADDE()
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| /external/qemu/tcg/ppc64/ |
| D | tcg-target.c | 336 #define ADDE XO31(138) macro
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 343 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 92 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 208 setOperationAction(ISD::ADDE, MVT::i64, Expand); in NVPTXTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 317 case ISD::ADDE: in IsProfitableToFold()
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| D | X86ISelLowering.cpp | 427 setOperationAction(ISD::ADDE, VT, Custom); in resetOperationActions()
12733 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
12871 case ISD::ADDE: in LowerOperation()
12937 case ISD::ADDE: in ReplaceNodeResults()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 2004 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
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| /external/chromium_org/third_party/icu/source/test/testdata/ |
| D | NormalizationTest-3.2.0.txt | 2731 ADDE;ADDE;1100 1172 11A9;ADDE;1100 1172 11A9;
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