Home
last modified time | relevance | path

Searched refs:BaseOffs (Results 1 – 13 of 13) sorted by relevance

/external/llvm/lib/Transforms/Scalar/
DCodeGenPrepare.cpp838 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && in operator ==()
858 if (BaseOffs) in print()
859 OS << (NeedPlus ? " + " : "") << BaseOffs, NeedPlus = true; in print()
978 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale; in MatchScaledValue()
1122 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
1128 AddrMode.BaseOffs -= ConstantOffset; in MatchOperationAddr()
1137 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
1162 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
1186 AddrMode.BaseOffs += CI->getSExtValue(); in MatchAddr()
1189 AddrMode.BaseOffs -= CI->getSExtValue(); in MatchAddr()
[all …]
/external/llvm/lib/Analysis/
DBasicAliasAnalysis.cpp274 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, in DecomposeGEPExpression() argument
280 BaseOffs = 0; in DecomposeGEPExpression()
341 BaseOffs += TD->getStructLayout(STy)->getElementOffset(FieldNo); in DecomposeGEPExpression()
348 BaseOffs += TD->getTypeAllocSize(*GTI)*CIdx->getSExtValue(); in DecomposeGEPExpression()
368 BaseOffs += IndexOffset.getSExtValue()*Scale; in DecomposeGEPExpression()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1599 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1605 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1612 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1615 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1620 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1623 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1627 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1630 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/external/llvm/lib/CodeGen/
DBasicTargetTransformInfo.cpp144 AM.BaseOffs = BaseOffset; in isLegalAddressingMode()
155 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
DTargetLoweringBase.cpp1285 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1297 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1302 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/include/llvm/Target/
DTargetLowering.h1108 int64_t BaseOffs; member
1111 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1638 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { in isLegalAddressingMode()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp7733 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
7745 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
7750 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1945 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale) in isLegalAddressingMode()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp301 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp6998 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
7006 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp10146 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
10162 if (AM.BaseOffs) in isLegalAddressingMode()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp13274 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) in isLegalAddressingMode()
13292 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()