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Searched refs:CP0SRSCtl_PSS (Results 1 – 3 of 3) sorted by relevance

/external/qemu/target-mips/
Dcpu.h297 #define CP0SRSCtl_PSS 6 macro
Dop_helper.c1201 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); in helper_mtc0_srsctl()
Dtranslate.c558 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); in gen_load_srsgpr()
581 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); in gen_store_srsgpr()