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Searched refs:CondCode (Results 1 – 25 of 75) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h709 enum CondCode { enum
742 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
748 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
755 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
763 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
769 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
773 CondCode getSetCCSwappedOperands(CondCode Operation);
779 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
785 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
DAnalysis.h72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
DSelectionDAG.h480 SDValue getCondCode(ISD::CondCode Cond);
608 ISD::CondCode Cond) {
634 SDValue True, SDValue False, ISD::CondCode Cond) {
1005 SDValue N2, ISD::CondCode Cond, SDLoc dl);
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp32 enum CondCode { enum
130 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
143 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
154 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
236 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in AnalyzeBranch()
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
395 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/
Dnv50_ir_inlines.h26 static inline CondCode reverseCondCode(CondCode cc) in reverseCondCode()
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); in reverseCondCode()
33 static inline CondCode inverseCondCode(CondCode cc) in inverseCondCode()
35 return static_cast<CondCode>(cc ^ 7); in inverseCondCode()
Dnv50_ir.h168 enum CondCode enum
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; } in setCondition()
827 CondCode getCondition() const { return setCond; } in getCondition()
830 CondCode setCond;
Dnv50_ir_build_util.h73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
Dnv50_ir_build_util.cpp223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst, in mkCmp()
307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred) in mkFlow()
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_inlines.h26 static inline CondCode reverseCondCode(CondCode cc) in reverseCondCode()
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); in reverseCondCode()
33 static inline CondCode inverseCondCode(CondCode cc) in inverseCondCode()
35 return static_cast<CondCode>(cc ^ 7); in inverseCondCode()
Dnv50_ir.h168 enum CondCode enum
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; } in setCondition()
827 CondCode getCondition() const { return setCond; } in getCondition()
830 CondCode setCond;
Dnv50_ir_build_util.h73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
Dnv50_ir_build_util.cpp223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst, in mkCmp()
307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred) in mkFlow()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h32 enum CondCode { enum
62 unsigned GetCondBranchFromCond(CondCode CC);
65 CondCode getCondFromCMovOpc(unsigned Opc);
69 CondCode GetOppositeBranchCondition(X86::CondCode CC);
DX86InstrInfo.cpp2371 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { in getCondFromBranchOpc()
2394 static X86::CondCode getCondFromSETOpc(unsigned Opc) { in getCondFromSETOpc()
2417 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { in getCondFromCMovOpc()
2471 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { in GetCondBranchFromCond()
2495 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { in GetOppositeBranchCondition()
2520 static X86::CondCode getSwappedCondition(X86::CondCode CC) { in getSwappedCondition()
2538 static unsigned getSETFromCond(X86::CondCode CC, in getSETFromCond()
2565 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, in getCMovFromCond()
2678 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); in AnalyzeBranch()
2740 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); in AnalyzeBranch()
[all …]
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.h33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
DMipsInstPrinter.cpp35 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
211 O << MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td495 class CondCode; // ISD::CondCode enums
496 def SETOEQ : CondCode; def SETOGT : CondCode;
497 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
498 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
499 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
500 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
502 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
503 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
DTargetLowering.h519 getCondCodeAction(ISD::CondCode CC, MVT VT) const { in getCondCodeAction()
533 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { in isCondCodeLegal()
1012 void setCondCodeAction(ISD::CondCode CC, MVT VT, in setCondCodeAction()
1240 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { in setCmpLibcallCC()
1246 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { in getCmpLibcallCC()
1574 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1703 ISD::CondCode &CCCode, SDLoc DL) const;
1804 ISD::CondCode Cond, bool foldBooleans,
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp628 unsigned CondCode = MI->getOperand(3).getImm(); in EmitF128CSEL() local
654 .addImm(CondCode) in EmitF128CSEL()
1595 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) { in IntCCToA64CC()
1623 ISD::CondCode CC, SDValue &A64cc, in getSelectableIntSetCC()
1678 A64CC::CondCodes CondCode = IntCCToA64CC(CC); in getSelectableIntSetCC() local
1679 A64cc = DAG.getConstant(CondCode, MVT::i32); in getSelectableIntSetCC()
1684 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC, in FPCCToA64CC()
1686 A64CC::CondCodes CondCode = A64CC::Invalid; in FPCCToA64CC() local
1692 case ISD::SETOEQ: CondCode = A64CC::EQ; break; in FPCCToA64CC()
1694 case ISD::SETOGT: CondCode = A64CC::GT; break; in FPCCToA64CC()
[all …]
DAArch64ISelLowering.h206 SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
/external/llvm/lib/CodeGen/
DAnalysis.cpp150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
172 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
187 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
472 ISD::CondCode CC, SDLoc dl) { in SelectCC()
569 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { in getPredicateForSetCC()
600 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { in getCRIdxForSetCC()
632 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { in getVCmpInst()
714 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SelectSETCC()
1181 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in Select()
1244 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); in Select()
1245 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
1246 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, in Select()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp203 struct CondCodeOp CondCode; member
242 return CondCode.Code; in getCondCode()
773 Op->CondCode.Code = Code; in CreateCondCode()
1443 A64CC::CondCodes CondCode = A64StringToCondCode(Tok); in ParseCondCodeOperand() local
1445 if (CondCode == A64CC::Invalid) in ParseCondCodeOperand()
1452 Operands.push_back(AArch64Operand::CreateCondCode(CondCode, S, E)); in ParseCondCodeOperand()
2252 OS << "<CondCode: " << CondCode.Code << ">"; in print()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp653 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in SoftenFloatOp_BR_CC()
699 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in SoftenFloatOp_SELECT_CC()
722 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SoftenFloatOp_SETCC()
1282 ISD::CondCode &CCCode, in FloatExpandSetCCOperands()
1312 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in ExpandFloatOp_BR_CC()
1394 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in ExpandFloatOp_SELECT_CC()
1412 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in ExpandFloatOp_SETCC()
DSelectionDAGBuilder.h197 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
207 ISD::CondCode CC;

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