Searched refs:DReg (Results 1 – 4 of 4) sorted by relevance
/external/llvm/lib/Target/ARM/ |
D | A15SDOptimizer.cpp | 79 unsigned DReg, unsigned Lane, 94 DebugLoc DL, unsigned DReg, unsigned Lane, 152 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local 154 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR() 453 unsigned DReg, unsigned Lane, in createExtractSubreg() argument 460 .addReg(DReg, 0, Lane); in createExtractSubreg() 504 DebugLoc DL, unsigned DReg, unsigned Lane, in createInsertSubreg() argument 511 .addReg(DReg) in createInsertSubreg()
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D | ARMBaseInstrInfo.cpp | 3768 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local 3771 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane() 3772 return DReg; in getCorrespondingDRegAndLane() 3775 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() 3777 assert(DReg && "S-register with no D super-register?"); in getCorrespondingDRegAndLane() 3778 return DReg; in getCorrespondingDRegAndLane() 3798 unsigned DReg, unsigned Lane, in getImplicitSPRUseForDPRUse() argument 3802 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse() 3808 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse() 3826 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local [all …]
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D | ARMExpandPseudoInsts.cpp | 1011 unsigned DReg = TRI->getMatchingSuperReg(SrcReg, in ExpandMI() local 1017 MIB.addReg(DReg); in ExpandMI()
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/external/llvm/lib/Target/X86/ |
D | X86FloatingPoint.cpp | 898 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local 899 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n"); in adjustLiveRegs() 900 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs() 901 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs() 903 Defs &= ~(1 << DReg); in adjustLiveRegs() 929 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local 930 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n"); in adjustLiveRegs() 932 pushReg(DReg); in adjustLiveRegs() 933 Defs &= ~(1 << DReg); in adjustLiveRegs()
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