| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 447 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
144 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
144 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 258 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
307 Opcode = ISD::FCEIL; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
157 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
161 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
413 setOperationAction(ISD::FCEIL, VT, Expand); in PPCTargetLowering()
459 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 707 setOperationAction(ISD::FCEIL, MVT::f16, Expand); in initActions()
717 setOperationAction(ISD::FCEIL, MVT::f32, Expand); in initActions()
727 setOperationAction(ISD::FCEIL, MVT::f64, Expand); in initActions()
737 setOperationAction(ISD::FCEIL, MVT::f128, Expand); in initActions()
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| D | BasicTargetTransformInfo.cpp | 447 case Intrinsic::ceil: ISD = ISD::FCEIL; break; in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 45 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 142 case ISD::FCEIL: return "fceil"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 240 case ISD::FCEIL: in LegalizeOp()
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| D | LegalizeFloatTypes.cpp | 70 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
802 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 72 case ISD::FCEIL: in ScalarizeVectorResult()
528 case ISD::FCEIL: in SplitVectorResult()
1499 case ISD::FCEIL: in WidenVectorResult()
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| D | SelectionDAGBuilder.cpp | 4914 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in visitIntrinsicCall()
5638 if (visitUnaryFloatCall(I, ISD::FCEIL)) in visitCall()
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| D | LegalizeDAG.cpp | 3217 case ISD::FCEIL: in ExpandNode()
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| D | DAGCombiner.cpp | 1166 case ISD::FCEIL: return visitFCEIL(N); in visit()
6726 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0); in visitFCEIL()
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| D | SelectionDAG.cpp | 2475 case ISD::FCEIL: { in getNode()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 150 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AArch64TargetLowering()
151 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in AArch64TargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 383 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 773 setOperationAction(ISD::FCEIL, MVT::f80, Expand); in resetOperationActions()
826 setOperationAction(ISD::FCEIL, VT, Expand); in resetOperationActions()
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in resetOperationActions()
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in resetOperationActions()
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in resetOperationActions()
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in resetOperationActions()
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal); in resetOperationActions()
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in resetOperationActions()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 502 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
519 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); in ARMTargetLowering()
536 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); in ARMTargetLowering()
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