| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 447 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 257 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in mightUseCTR()
299 Opcode = ISD::FFLOOR; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
156 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
160 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
412 setOperationAction(ISD::FFLOOR, VT, Expand); in PPCTargetLowering()
458 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 705 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); in initActions()
715 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); in initActions()
725 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); in initActions()
735 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); in initActions()
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| D | BasicTargetTransformInfo.cpp | 446 case Intrinsic::floor: ISD = ISD::FFLOOR; break; in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 141 case ISD::FFLOOR: return "ffloor"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 244 case ISD::FFLOOR: in LegalizeOp()
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| D | LegalizeFloatTypes.cpp | 76 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; in SoftenFloatResult()
808 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 76 case ISD::FFLOOR: in ScalarizeVectorResult()
532 case ISD::FFLOOR: in SplitVectorResult()
1503 case ISD::FFLOOR: in WidenVectorResult()
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| D | SelectionDAGBuilder.cpp | 4913 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in visitIntrinsicCall()
5626 if (visitUnaryFloatCall(I, ISD::FFLOOR)) in visitCall()
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| D | LegalizeDAG.cpp | 3212 case ISD::FFLOOR: in ExpandNode()
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| D | DAGCombiner.cpp | 1165 case ISD::FFLOOR: return visitFFLOOR(N); in visit()
6750 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0); in visitFFLOOR()
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| D | SelectionDAG.cpp | 2487 case ISD::FFLOOR: { in getNode()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 153 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AArch64TargetLowering()
154 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in AArch64TargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 384 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); in resetOperationActions()
825 setOperationAction(ISD::FFLOOR, VT, Expand); in resetOperationActions()
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in resetOperationActions()
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in resetOperationActions()
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in resetOperationActions()
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in resetOperationActions()
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal); in resetOperationActions()
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); in resetOperationActions()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 506 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); in ARMTargetLowering()
523 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand); in ARMTargetLowering()
540 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand); in ARMTargetLowering()
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