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Searched refs:ISD (Results 1 – 25 of 139) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp36 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
54 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
56 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
57 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
58 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
59 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
60 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
61 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
62 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; in getOperationName()
63 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; in getOperationName()
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DLegalizeVectorOps.cpp154 if (Op.getOpcode() == ISD::LOAD) { in LegalizeOp()
156 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
157 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { in LegalizeOp()
163 } else if (Op.getOpcode() == ISD::STORE) { in LegalizeOp()
193 case ISD::ADD: in LegalizeOp()
194 case ISD::SUB: in LegalizeOp()
195 case ISD::MUL: in LegalizeOp()
196 case ISD::SDIV: in LegalizeOp()
197 case ISD::UDIV: in LegalizeOp()
198 case ISD::SREM: in LegalizeOp()
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DLegalizeIntegerTypes.cpp50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
57 case ISD::CONVERT_RNDSAT: in PromoteIntegerResult()
59 case ISD::CTLZ_ZERO_UNDEF: in PromoteIntegerResult()
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
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DLegalizeDAG.cpp277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && in ExpandConstantFP()
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, in ExpandConstantFP()
307 assert(ST->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedStore()
322 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
363 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
365 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
375 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
387 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], in ExpandUnalignedStore()
404 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
411 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
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DTargetLowering.cpp104 ISD::CondCode &CCCode, in softenSetCCOperands()
112 case ISD::SETEQ: in softenSetCCOperands()
113 case ISD::SETOEQ: in softenSetCCOperands()
117 case ISD::SETNE: in softenSetCCOperands()
118 case ISD::SETUNE: in softenSetCCOperands()
122 case ISD::SETGE: in softenSetCCOperands()
123 case ISD::SETOGE: in softenSetCCOperands()
127 case ISD::SETLT: in softenSetCCOperands()
128 case ISD::SETOLT: in softenSetCCOperands()
132 case ISD::SETLE: in softenSetCCOperands()
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DLegalizeVectorTypes.cpp49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; in ScalarizeVectorResult()
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; in ScalarizeVectorResult()
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; in ScalarizeVectorResult()
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DDAGCombiner.cpp159 ISD::NodeType ExtType);
257 SDValue N3, ISD::CondCode CC,
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
411 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
421 case ISD::ConstantFP: in isNegatibleForFree()
425 case ISD::FADD: in isNegatibleForFree()
431 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) in isNegatibleForFree()
441 case ISD::FSUB: in isNegatibleForFree()
448 case ISD::FMUL: in isNegatibleForFree()
449 case ISD::FDIV: in isNegatibleForFree()
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DSelectionDAG.cpp97 bool ISD::isBuildVectorAllOnes(const SDNode *N) { in isBuildVectorAllOnes()
99 if (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllOnes()
102 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllOnes()
107 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllOnes()
137 N->getOperand(i).getOpcode() != ISD::UNDEF) in isBuildVectorAllOnes()
145 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros()
147 if (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllZeros()
150 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllZeros()
155 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllZeros()
177 N->getOperand(i).getOpcode() != ISD::UNDEF) in isBuildVectorAllZeros()
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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp181 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
182 assert(ISD && "Invalid opcode"); in getCastInstrCost()
187 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
188 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
189 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
192 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
193 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
196 ISD, LT.second); in getCastInstrCost()
211 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
212 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp174 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
175 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
180 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
181 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
182 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
183 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
184 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
185 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
186 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
187 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
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DX86ISelLowering.cpp73 if (Vec.getOpcode() == ISD::UNDEF) in ExtractSubVector()
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR) in ExtractSubVector()
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, in ExtractSubVector()
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, in ExtractSubVector()
122 if (Vec.getOpcode() == ISD::UNDEF) in InsertSubVector()
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, in InsertSubVector()
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in resetOperationActions()
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in resetOperationActions()
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in resetOperationActions()
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); in resetOperationActions()
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/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
47 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in AMDGPUTargetLowering()
49 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
51 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
54 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AMDGPUTargetLowering()
58 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
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DAMDILISelLowering.cpp99 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
100 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
101 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
102 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
103 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
104 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
105 setOperationAction(ISD::BR_JT, VT, Expand); in InitAMDILLowering()
106 setOperationAction(ISD::BRIND, VT, Expand); in InitAMDILLowering()
108 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
109 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in InitAMDILLowering()
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
112 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
114 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
115 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
116 setOperationAction(ISD::BR_JT, VT, Expand); in InitAMDILLowering()
117 setOperationAction(ISD::BRIND, VT, Expand); in InitAMDILLowering()
119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in InitAMDILLowering()
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DAMDGPUISelLowering.cpp31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
37 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
39 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AMDGPUTargetLowering()
41 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
52 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
68 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
89 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
112 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
114 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
115 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
116 setOperationAction(ISD::BR_JT, VT, Expand); in InitAMDILLowering()
117 setOperationAction(ISD::BRIND, VT, Expand); in InitAMDILLowering()
119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in InitAMDILLowering()
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DAMDGPUISelLowering.cpp31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
37 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
39 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AMDGPUTargetLowering()
41 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
52 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
68 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
89 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp54 ISD::ArgFlagsTy ArgFlags, CCState &State);
59 ISD::ArgFlagsTy ArgFlags, CCState &State);
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
69 ISD::ArgFlagsTy ArgFlags, CCState &State);
74 ISD::ArgFlagsTy ArgFlags, CCState &State);
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
84 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon_VarArg()
133 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon()
171 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon32()
189 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon64()
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/external/llvm/lib/CodeGen/
DBasicTargetTransformInfo.cpp181 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in shouldBuildLookupTables()
182 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); in shouldBuildLookupTables()
223 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
224 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
233 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) { in getArithmeticInstrCost()
243 if (!TLI->isOperationExpand(ISD, LT.second)) { in getArithmeticInstrCost()
270 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
271 assert(ISD && "Invalid opcode"); in getCastInstrCost()
294 if (TLI->isOperationLegalOrPromote(ISD, DstLT.second)) in getCastInstrCost()
305 if (!TLI->isOperationExpand(ISD, DstLT.second)) in getCastInstrCost()
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DTargetLoweringBase.cpp591 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { in InitCmpLibcallCCs()
592 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); in InitCmpLibcallCCs()
593 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
594 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
595 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
596 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
597 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
598 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
599 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
600 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
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DAnalysis.cpp150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
152 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE; in getFCmpCondCode()
153 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; in getFCmpCondCode()
154 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode()
155 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode()
156 case FCmpInst::FCMP_OLT: return ISD::SETOLT; in getFCmpCondCode()
157 case FCmpInst::FCMP_OLE: return ISD::SETOLE; in getFCmpCondCode()
158 case FCmpInst::FCMP_ONE: return ISD::SETONE; in getFCmpCondCode()
159 case FCmpInst::FCMP_ORD: return ISD::SETO; in getFCmpCondCode()
160 case FCmpInst::FCMP_UNO: return ISD::SETUO; in getFCmpCondCode()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MSP430TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); in MSP430TargetLowering()
95 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
96 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp76 setTargetDAGCombine(ISD::OR); in AArch64TargetLowering()
78 setTargetDAGCombine(ISD::AND); in AArch64TargetLowering()
79 setTargetDAGCombine(ISD::SRA); in AArch64TargetLowering()
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
84 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
87 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); in AArch64TargetLowering()
88 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in AArch64TargetLowering()
89 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in AArch64TargetLowering()
92 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in AArch64TargetLowering()
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp39 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
52 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_f64()
81 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
120 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
165 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
176 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
239 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
274 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
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/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
126 if (N.getOpcode() == ISD::TargetConstant || in SelectAddrImmOffs()
127 N.getOpcode() == ISD::TargetGlobalAddress) { in SelectAddrImmOffs()
282 if (N->getOpcode() != ISD::Constant) in isIntS16Immediate()
300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { in isInt64Immediate()
371 if (Opcode == ISD::SHL) { in isRotateAndMask()
376 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
383 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
421 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { in SelectBitfieldInsert()
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