Searched refs:ImmS (Results 1 – 6 of 6) sorted by relevance
/external/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.cpp | 1005 uint32_t ImmS = Num1s - 1; in isLogicalImm() local 1009 case 16: ImmS |= 0x20; break; // 10ssss in isLogicalImm() 1010 case 8: ImmS |= 0x30; break; // 110sss in isLogicalImm() 1011 case 4: ImmS |= 0x38; break; // 1110ss in isLogicalImm() 1012 case 2: ImmS |= 0x3c; break; // 11110s in isLogicalImm() 1015 Bits = ImmS | (ImmR << 6) | (N << 12); in isLogicalImm() 1025 uint32_t ImmS = Bits & 0x3f; in isLogicalImmBits() local 1034 else if ((ImmS & 0x20) == 0) in isLogicalImmBits() 1036 else if ((ImmS & 0x10) == 0) in isLogicalImmBits() 1038 else if ((ImmS & 0x08) == 0) in isLogicalImmBits() [all …]
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/external/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64Disassembler.cpp | 476 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); in DecodeBitfieldInstruction() local 487 if (ImmR > 31 || ImmS > 31) in DecodeBitfieldInstruction() 504 assert(!(ImmS == 31 && !SF && Opc != BFM) in DecodeBitfieldInstruction() 506 assert(!(ImmS == 63 && SF && Opc != BFM) in DecodeBitfieldInstruction() 511 assert((ImmS != 7 && ImmS != 15) && "extension got here"); in DecodeBitfieldInstruction() 512 assert((ImmS != 31 || SF == 0) && "extension got here"); in DecodeBitfieldInstruction() 514 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here"); in DecodeBitfieldInstruction() 520 if (SF && (ImmS + 1) % 64 == ImmR) { in DecodeBitfieldInstruction() 522 Inst.addOperand(MCOperand::CreateImm(63 - ImmS)); in DecodeBitfieldInstruction() 524 } else if (!SF && (ImmS + 1) % 32 == ImmR) { in DecodeBitfieldInstruction() [all …]
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
D | AArch64InstPrinter.cpp | 146 unsigned ImmS = ImmSOp.getImm(); in printBFXWidthOperand() local 148 assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract"); in printBFXWidthOperand() 150 O << '#' << (ImmS - ImmR + 1); in printBFXWidthOperand()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 118 // (A64[SU]BFX Field, ImmR, ImmS). 120 // Note that ImmR and ImmS are already encoded for the actual instructions. The 121 // more natural LSB and Width mix together to form ImmR and ImmS, something 1032 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1033 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1039 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1040 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1053 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1054 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1061 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), [all …]
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D | AArch64InstrFormats.td | 204 bits<6> ImmS; 211 let Inst{15-10} = ImmS; 820 bits<6> ImmS; 822 // N, ImmR and ImmS have no separate existence in any assembly syntax (or for 827 // ImmS = Imm{5-0};
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/external/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 1840 int64_t ImmS = Inst.getOperand(ImmOps+1).getImm(); in validateInstruction() local 1842 if (ImmR != 0 && ImmS >= ImmR) { in validateInstruction() 1856 int64_t ImmS = Inst.getOperand(ImmOps+1).getImm(); in validateInstruction() local 1867 if (ImmS >= RegWidth || ImmS < ImmR) { in validateInstruction()
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