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Searched refs:LoadedVT (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp394 EVT LoadedVT = LD->getMemoryVT(); in SelectBaseOffsetLoad() local
396 if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) { in SelectBaseOffsetLoad()
406 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed; in SelectBaseOffsetLoad()
407 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed; in SelectBaseOffsetLoad()
408 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed; in SelectBaseOffsetLoad()
409 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed; in SelectBaseOffsetLoad()
437 EVT LoadedVT = LD->getMemoryVT(); in SelectIndexedLoadSignExtend64() local
450 if (TII->isValidAutoIncImm(LoadedVT, Val)) { in SelectIndexedLoadSignExtend64()
504 EVT LoadedVT = LD->getMemoryVT(); in SelectIndexedLoadZeroExtend64() local
517 if (TII->isValidAutoIncImm(LoadedVT, Val)) { in SelectIndexedLoadZeroExtend64()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1016 EVT LoadedVT = LD->getMemoryVT(); in Select() local
1030 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
1031 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
1042 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
1043 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
1064 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
1065 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
1076 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
1078 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp195 EVT LoadedVT = LD->getMemoryVT(); in SelectLoad() local
202 if (!LoadedVT.isSimple()) in SelectLoad()
217 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
436 EVT LoadedVT = MemSD->getMemoryVT(); in SelectLoadVector() local
438 if (!LoadedVT.isSimple()) in SelectLoadVector()
453 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoadVector()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1462 EVT LoadedVT = LD->getMemoryVT(); in SelectARMIndexedLoad() local
1467 if (LoadedVT == MVT::i32 && isPre && in SelectARMIndexedLoad()
1471 } else if (LoadedVT == MVT::i32 && !isPre && in SelectARMIndexedLoad()
1475 } else if (LoadedVT == MVT::i32 && in SelectARMIndexedLoad()
1480 } else if (LoadedVT == MVT::i16 && in SelectARMIndexedLoad()
1486 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { in SelectARMIndexedLoad()
1535 EVT LoadedVT = LD->getMemoryVT(); in SelectT2IndexedLoad() local
1542 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp434 EVT LoadedVT = LD->getMemoryVT(); in ExpandUnalignedLoad() local
437 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in ExpandUnalignedLoad()
438 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) { in ExpandUnalignedLoad()
445 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in ExpandUnalignedLoad()
446 if (LoadedVT != VT) in ExpandUnalignedLoad()
458 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
463 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in ExpandUnalignedLoad()
509 MachinePointerInfo(), LoadedVT, false, false, 0); in ExpandUnalignedLoad()
516 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && in ExpandUnalignedLoad()
521 unsigned NumBits = LoadedVT.getSizeInBits(); in ExpandUnalignedLoad()
DDAGCombiner.cpp2768 EVT LoadedVT = LN0->getMemoryVT(); in visitAND() local
2770 if (ExtVT == LoadedVT && in visitAND()
2788 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && in visitAND()
2799 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); in visitAND()