| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 33 class MCOperand {
53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
111 static MCOperand CreateReg(unsigned Reg) { in CreateReg()
112 MCOperand Op; in CreateReg()
117 static MCOperand CreateImm(int64_t Val) { in CreateImm()
118 MCOperand Op; in CreateImm()
123 static MCOperand CreateFPImm(double Val) { in CreateFPImm()
124 MCOperand Op; in CreateFPImm()
129 static MCOperand CreateExpr(const MCExpr *Val) { in CreateExpr()
130 MCOperand Op; in CreateExpr()
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| D | MCInstBuilder.h | 33 Inst.addOperand(MCOperand::CreateReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::CreateImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::CreateFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::CreateExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::CreateInst(Val)); in addInst()
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
284 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
287 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
290 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
322 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
353 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
383 MCOperand baseReg; in translateRMMemory()
384 MCOperand scaleAmount; in translateRMMemory()
385 MCOperand indexReg; in translateRMMemory()
386 MCOperand displacement; in translateRMMemory()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 55 const MCOperand &MOImm = MI->getOperand(OpNum); in printOffsetSImm9Operand()
94 const MCOperand &Imm12Op = MI->getOperand(OpNum); in printAddSubImmLSL0Operand()
118 const MCOperand &MO = MI->getOperand(OpNum); in printBareImmOperand()
125 const MCOperand &ImmROp = MI->getOperand(OpNum); in printBFILSBOperand()
133 const MCOperand &ImmSOp = MI->getOperand(OpNum); in printBFIWidthOperand()
142 const MCOperand &ImmSOp = MI->getOperand(OpNum); in printBFXWidthOperand()
143 const MCOperand &ImmROp = MI->getOperand(OpNum - 1); in printBFXWidthOperand()
156 const MCOperand &CRx = MI->getOperand(OpNum); in printCRxOperand()
165 const MCOperand &ScaleOp = MI->getOperand(OpNum); in printCVTFixedPosOperand()
173 const MCOperand &MOImm8 = MI->getOperand(OpNum); in printFPImmOperand()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 103 const MCOperand &Dst = MI->getOperand(0); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst()
106 const MCOperand &MO3 = MI->getOperand(3); in printInst()
126 const MCOperand &Dst = MI->getOperand(0); in printInst()
127 const MCOperand &MO1 = MI->getOperand(1); in printInst()
128 const MCOperand &MO2 = MI->getOperand(2); in printInst()
258 MCOperand NewReg; in printInst()
263 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0, in printInst()
281 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
419 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
449 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
450 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
478 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
514 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLTargetOpValue()
526 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLXTargetOpValue()
537 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBRTargetOpValue()
548 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBCCTargetOpValue()
559 const MCOperand MO = MI.getOperand(OpIdx); in getThumbCBTargetOpValue()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreMCInstLower.cpp | 35 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
71 return MCOperand::CreateExpr(MCSym); in LowerSymbolOperand()
78 return MCOperand::CreateExpr(Add); in LowerSymbolOperand()
81 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
90 return MCOperand::CreateReg(MO.getReg()); in LowerOperand()
92 return MCOperand::CreateImm(MO.getImm() + offset); in LowerOperand()
104 return MCOperand(); in LowerOperand()
112 MCOperand MCOp = LowerOperand(MO); in Lower()
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 347 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeGPR64RegisterClass()
358 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeGPR32RegisterClass()
377 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeFGR64RegisterClass()
389 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeFGR32RegisterClass()
400 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeCCRRegisterClass()
411 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeFCCRegisterClass()
427 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeMem()
430 Inst.addOperand(MCOperand::CreateReg(Reg)); in DecodeMem()
431 Inst.addOperand(MCOperand::CreateReg(Base)); in DecodeMem()
432 Inst.addOperand(MCOperand::CreateImm(Offset)); in DecodeMem()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMMCInstLower.cpp | 26 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO, in GetSymbolRef()
62 return MCOperand::CreateExpr(Expr); in GetSymbolRef()
67 MCOperand &MCOp) { in lowerOperand()
75 MCOp = MCOperand::CreateReg(MO.getReg()); in lowerOperand()
78 MCOp = MCOperand::CreateImm(MO.getImm()); in lowerOperand()
81 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( in lowerOperand()
104 MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); in lowerOperand()
121 MCOperand MCOp; in LowerARMMachineInstrToMCInst()
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| D | ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::CreateImm(0)); in getNoopForMachoTarget()
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in getNoopForMachoTarget()
41 NopInst.addOperand(MCOperand::CreateReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); in getNoopForMachoTarget()
46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::CreateReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::CreateReg(0)); in getNoopForMachoTarget()
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 59 Inst.addOperand(MCOperand::CreateReg(RegNo)); in decodeRegisterClass()
108 Inst.addOperand(MCOperand::CreateImm(Imm)); in decodeUImmOperand()
115 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
169 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm) * 2 + Address)); in decodePCDBLOperand()
190 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
191 Inst.addOperand(MCOperand::CreateImm(Disp)); in decodeBDAddr12Operand()
200 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
201 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
211 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
212 Inst.addOperand(MCOperand::CreateImm(Disp)); in decodeBDXAddr12Operand()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMCInstLower.cpp | 27 static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol, in GetSymbolRef()
38 return (MCOperand::CreateExpr(ME)); in GetSymbolRef()
49 MCOperand MCO; in HexagonLowerToMC()
58 MCO = MCOperand::CreateReg(MO.getReg()); in HexagonLowerToMC()
64 MCO = MCOperand::CreateImm(*Val.bitcastToAPInt().getRawData()); in HexagonLowerToMC()
68 MCO = MCOperand::CreateImm(MO.getImm()); in HexagonLowerToMC()
71 MCO = MCOperand::CreateExpr in HexagonLowerToMC()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 391 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); in addRegGPRCOperands()
396 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
401 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); in addRegG8RCOperands()
406 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
425 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); in addRegF4RCOperands()
430 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); in addRegF8RCOperands()
435 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); in addRegVRRCOperands()
440 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()])); in addRegCRBITRCOperands()
445 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()])); in addRegCRRCOperands()
450 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()])); in addCRBitMaskOperands()
[all …]
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 252 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR64RegisterClass()
263 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR64xspRegisterClass()
274 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR32RegisterClass()
285 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPR32wspRegisterClass()
296 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR8RegisterClass()
307 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR16RegisterClass()
319 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR32RegisterClass()
330 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR64RegisterClass()
342 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeFPR128RegisterClass()
353 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeVPR64RegisterClass()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64MCInstLower.cpp | 30 MCOperand
96 return MCOperand::CreateExpr(Expr); in lowerSymbolOperand()
100 MCOperand &MCOp) const { in lowerOperand()
107 MCOp = MCOperand::CreateReg(MO.getReg()); in lowerOperand()
110 MCOp = MCOperand::CreateImm(MO.getImm()); in lowerOperand()
114 MCOp = MCOperand::CreateFPImm(0.0); in lowerOperand()
127 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( in lowerOperand()
153 MCOperand MCOp; in LowerAArch64MachineInstrToMCInst()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 277 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
283 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
285 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
287 Inst.addOperand(MCOperand::CreateExpr(Expr)); in addExpr()
299 Inst.addOperand(MCOperand::CreateReg(getMemBase())); in addMemOperands()
379 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); in addRegAsmOperands()
453 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); in processInstruction()
454 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); in processInstruction()
455 NopInst.addOperand(MCOperand::CreateImm(0)); in processInstruction()
467 MCOperand &Op = Inst.getOperand(i); in processInstruction()
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
112 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
123 const MCOperand &MO = MI.getOperand(OpNo); in getCondBrEncoding()
135 const MCOperand &MO = MI.getOperand(OpNo); in getAbsDirectBrEncoding()
147 const MCOperand &MO = MI.getOperand(OpNo); in getAbsCondBrEncoding()
158 const MCOperand &MO = MI.getOperand(OpNo); in getImm16Encoding()
174 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIEncoding()
192 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIXEncoding()
205 const MCOperand &MO = MI.getOperand(OpNo); in getTLSRegEncoding()
221 const MCOperand &MO = MI.getOperand(OpNo+1); in getTLSCallEncoding()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMCInstLower.cpp | 36 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
107 return MCOperand::CreateExpr(MCSym); in LowerSymbolOperand()
114 return MCOperand::CreateExpr(Add); in LowerSymbolOperand()
129 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
138 return MCOperand::CreateReg(MO.getReg()); in LowerOperand()
140 return MCOperand::CreateImm(MO.getImm() + offset); in LowerOperand()
152 return MCOperand(); in LowerOperand()
160 MCOperand MCOp = LowerOperand(MO); in Lower()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUMCInstLower.cpp | 39 MCOperand MCOp; in lower()
47 MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat()); in lower()
51 MCOp = MCOperand::CreateImm(MO.getImm()); in lower()
54 MCOp = MCOperand::CreateReg(MO.getReg()); in lower()
57 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( in lower()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 1488 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
1490 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
1492 Inst.addOperand(MCOperand::CreateExpr(Expr)); in addExpr()
1497 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
1499 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1504 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocNumOperands()
1509 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocRegOperands()
1514 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); in addCoprocOptionOperands()
1519 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); in addITMaskOperands()
1524 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addITCondCodeOperands()
[all …]
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430MCInstLower.cpp | 91 MCOperand MSP430MCInstLower::
106 return MCOperand::CreateExpr(Expr); in LowerSymbolOperand()
115 MCOperand MCOp; in Lower()
123 MCOp = MCOperand::CreateReg(MO.getReg()); in Lower()
126 MCOp = MCOperand::CreateImm(MO.getImm()); in Lower()
129 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( in Lower()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 49 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
158 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
224 return MCOperand::CreateExpr(Expr); in LowerSymbolOperand()
251 MCOperand Saved = Inst.getOperand(ImmOp); in SimplifyShortImmForm()
330 MCOperand Saved = Inst.getOperand(AddrOp); in SimplifyShortMoveForm()
342 MCOperand MCOp; in Lower()
350 MCOp = MCOperand::CreateReg(MO.getReg()); in Lower()
353 MCOp = MCOperand::CreateImm(MO.getImm()); in Lower()
455 MCOperand Saved = OutMI.getOperand(0); in Lower()
481 MCOperand Saved = OutMI.getOperand(0); in Lower()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 566 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
571 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
630 I = MI.insert(I, MCOperand::CreateImm(CC)); in AddThumbPredicate()
633 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
635 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
640 I = MI.insert(I, MCOperand::CreateImm(CC)); in AddThumbPredicate()
643 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
645 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
864 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPRRegisterClass()
888 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 77 unsigned getAddressWithFixup(const MCOperand &MO,
89 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
121 unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO, in getAddressWithFixup()
143 const MCOperand &ImmOp = MI.getOperand(OpIdx); in getOffsetUImm12OpValue()
228 const MCOperand &MO = MI.getOperand(OpIdx); in getAddSubImmOpValue()
262 const MCOperand &MO = MI.getOperand(OpIdx); in getAdrpLabelOpValue()
297 const MCOperand &MO = MI.getOperand(OpIdx); in getBitfield32LSLOpValue()
307 const MCOperand &MO = MI.getOperand(OpIdx); in getBitfield64LSLOpValue()
318 const MCOperand &MO = MI.getOperand(OpIdx); in getLabelOpValue()
331 const MCOperand &MO = MI.getOperand(OpIdx); in getLoadLitLabelOpValue()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZMCInstLower.cpp | 42 MCOperand SystemZMCInstLower::lowerSymbolOperand(const MachineOperand &MO, in lowerSymbolOperand()
51 return MCOperand::CreateExpr(Expr); in lowerSymbolOperand()
54 MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const { in lowerOperand()
60 return MCOperand::CreateReg(MO.getReg()); in lowerOperand()
63 return MCOperand::CreateImm(MO.getImm()); in lowerOperand()
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