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Searched refs:NumOps (Results 1 – 25 of 56) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86CodeEmitter.cpp172 unsigned NumOps = Desc.getNumOperands(); in determineREX() local
173 if (NumOps) { in determineREX()
174 bool isTwoAddr = NumOps > 1 && in determineREX()
179 for (unsigned e = NumOps; i != e; ++i) { in determineREX()
197 for (unsigned e = NumOps; i != e; ++i) { in determineREX()
209 for (; i != NumOps; ++i) { in determineREX()
226 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e))) in determineREX()
243 for (unsigned e = NumOps; i != e; ++i) { in determineREX()
931 unsigned NumOps = Desc->getNumOperands(); in emitVEXOpcodePrefix() local
933 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0) in emitVEXOpcodePrefix()
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DX86FloatingPoint.cpp986 unsigned NumOps = MI->getDesc().getNumOperands(); in handleOneArgFP() local
987 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) && in handleOneArgFP()
991 unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); in handleOneArgFP()
1023 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand in handleOneArgFP()
1051 unsigned NumOps = MI->getDesc().getNumOperands(); in handleOneArgFPRW() local
1052 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); in handleOneArgFPRW()
1473 unsigned NumOps = 0; in handleSpecialFP() local
1475 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) { in handleSpecialFP()
1477 NumOps = InlineAsm::getNumOperandRegisters(Flags); in handleSpecialFP()
1478 if (NumOps != 1) in handleSpecialFP()
/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp141 unsigned NumOps = MI->getNumOperands(); in verifyUseList() local
142 if (!(MO >= MO0 && MO < MO0+NumOps)) { in verifyUseList()
245 unsigned NumOps) { in moveOperands() argument
246 assert(Src != Dst && NumOps && "Noop moveOperands"); in moveOperands()
250 if (Dst >= Src && Dst < Src + NumOps) { in moveOperands()
252 Dst += NumOps - 1; in moveOperands()
253 Src += NumOps - 1; in moveOperands()
282 } while (--NumOps); in moveOperands()
DCallingConvLower.cpp120 unsigned NumOps = Outs.size(); in AnalyzeCallOperands() local
121 for (unsigned i = 0; i != NumOps; ++i) { in AnalyzeCallOperands()
139 unsigned NumOps = ArgVTs.size(); in AnalyzeCallOperands() local
140 for (unsigned i = 0; i != NumOps; ++i) { in AnalyzeCallOperands()
DMachineInstr.cpp538 if (unsigned NumOps = MCID->getNumOperands() + in MachineInstr() local
540 CapOperands = OperandCapacity::get(NumOps); in MachineInstr()
604 unsigned NumOps, MachineRegisterInfo *MRI) { in moveOperands() argument
606 return MRI->moveOperands(Dst, Src, NumOps); in moveOperands()
611 for (unsigned i = 0; i != NumOps; ++i) in moveOperands()
614 for (unsigned i = NumOps; i ; --i) in moveOperands()
929 unsigned NumOps; in findInlineAsmFlagIdx() local
931 i += NumOps) { in findInlineAsmFlagIdx()
936 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); in findInlineAsmFlagIdx()
937 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h566 unsigned NumOps = Desc.getNumOperands(); in getOperandBias() local
568 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
570 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
575 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
576 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) in getOperandBias()
580 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) in getOperandBias()
DX86MCCodeEmitter.cpp677 unsigned NumOps = Desc.getNumOperands(); in EmitVEXOpcodePrefix() local
679 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in EmitVEXOpcodePrefix()
681 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in EmitVEXOpcodePrefix()
686 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in EmitVEXOpcodePrefix()
687 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) in EmitVEXOpcodePrefix()
691 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) in EmitVEXOpcodePrefix()
956 unsigned NumOps = MI.getNumOperands(); in DetermineREXPrefix() local
958 bool isTwoAddr = NumOps > 1 && in DetermineREXPrefix()
963 for (; i != NumOps; ++i) { in DetermineREXPrefix()
981 for (; i != NumOps; ++i) { in DetermineREXPrefix()
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/external/llvm/lib/Target/Hexagon/
DHexagonCallingConvLower.cpp136 unsigned NumOps = Outs.size(); in AnalyzeCallOperands() local
146 for (; i != NumOps; ++i) { in AnalyzeCallOperands()
164 unsigned NumOps = ArgVTs.size(); in AnalyzeCallOperands() local
165 for (unsigned i = 0; i != NumOps; ++i) { in AnalyzeCallOperands()
/external/llvm/include/llvm/IR/
DConstant.h47 Constant(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps) in Constant() argument
48 : User(ty, vty, Ops, NumOps) {} in Constant()
DInlineAsm.h233 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
234 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
236 return Kind | (NumOps << 3);
DUser.h52 User(Type *ty, unsigned vty, Use *OpList, unsigned NumOps) in User() argument
53 : Value(ty, vty), OperandList(OpList), NumOperands(NumOps) {} in User()
DGlobalValue.h60 GlobalValue(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps, in GlobalValue() argument
62 : Constant(ty, vty, Ops, NumOps), Linkage(linkage), in GlobalValue()
DInstruction.h445 Instruction(Type *Ty, unsigned iType, Use *Ops, unsigned NumOps,
447 Instruction(Type *Ty, unsigned iType, Use *Ops, unsigned NumOps,
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h562 const SDUse *Ops, unsigned NumOps);
564 const SDValue *Ops, unsigned NumOps);
567 const SDValue *Ops, unsigned NumOps);
569 const SDValue *Ops, unsigned NumOps);
571 const SDValue *Ops, unsigned NumOps);
686 const SDValue *Ops, unsigned NumOps,
692 const SDValue *Ops, unsigned NumOps,
698 const SDValue *Ops, unsigned NumOps,
702 SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, SDLoc dl);
773 const SDValue *Ops, unsigned NumOps);
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DSelectionDAGNodes.h700 const SDValue *Ops, unsigned NumOps)
703 OperandList(NumOps ? new SDUse[NumOps] : 0),
705 NumOperands(NumOps), NumValues(VTs.NumVTs),
707 for (unsigned i = 0; i != NumOps; ++i) {
970 unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO);
1152 const SDValue *Ops, unsigned NumOps,
1154 : MemSDNode(Opc, Order, dl, VTs, Ops, NumOps, MemoryVT, MMO) {
1610 unsigned NumOps, ISD::CvtCode Code)
1611 : SDNode(ISD::CONVERT_RNDSAT, Order, dl, getSDVTList(VT), Ops, NumOps),
1613 assert(NumOps == 5 && "wrong number of operations");
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp338 const SDValue *Ops, unsigned NumOps) { in AddNodeIDOperands() argument
339 for (; NumOps; --NumOps, ++Ops) { in AddNodeIDOperands()
348 const SDUse *Ops, unsigned NumOps) { in AddNodeIDOperands() argument
349 for (; NumOps; --NumOps, ++Ops) { in AddNodeIDOperands()
770 const SDValue *Ops,unsigned NumOps, in FindModifiedNodeSlot() argument
776 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); in FindModifiedNodeSlot()
4269 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, in getMergeValues() argument
4271 if (NumOps == 1) in getMergeValues()
4275 VTs.reserve(NumOps); in getMergeValues()
4276 for (unsigned i = 0; i < NumOps; ++i) in getMergeValues()
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DScheduleDAGFast.cpp487 unsigned NumOps = Node->getNumOperands(); in DelayForLiveRegsBottomUp() local
488 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) in DelayForLiveRegsBottomUp()
489 --NumOps; // Ignore the glue operand. in DelayForLiveRegsBottomUp()
491 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { in DelayForLiveRegsBottomUp()
674 unsigned NumOps = N->getNumOperands(); in ScheduleNode() local
675 if (unsigned NumLeft = NumOps) { in ScheduleNode()
681 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) { in ScheduleNode()
DLegalizeTypes.cpp415 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i) in run() local
1024 unsigned NumOps = N->getNumOperands(); in LibCallify() local
1026 if (NumOps == 0) { in LibCallify()
1028 } else if (NumOps == 1) { in LibCallify()
1031 } else if (NumOps == 2) { in LibCallify()
1035 SmallVector<SDValue, 8> Ops(NumOps); in LibCallify()
1036 for (unsigned i = 0; i < NumOps; ++i) in LibCallify()
1040 &Ops[0], NumOps, isSigned, dl); in LibCallify()
DInstrEmitter.cpp598 unsigned NumOps = Node->getNumOperands(); in EmitRegSequence() local
599 assert((NumOps & 1) == 1 && in EmitRegSequence()
601 for (unsigned i = 1; i != NumOps; ++i) { in EmitRegSequence()
889 unsigned NumOps = Node->getNumOperands(); in EmitSpecialNode() local
890 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) in EmitSpecialNode()
891 --NumOps; // Ignore the glue operand. in EmitSpecialNode()
913 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { in EmitSpecialNode()
/external/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp702 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr() local
703 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
704 if (HasCC && MI->getOperand(NumOps-1).isDead()) in ReduceTo2Addr()
728 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr() local
730 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
798 unsigned NumOps = MCID.getNumOperands(); in ReduceToNarrow() local
799 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
800 if (HasCC && MI->getOperand(NumOps-1).isDead()) in ReduceToNarrow()
824 unsigned NumOps = MCID.getNumOperands(); in ReduceToNarrow() local
826 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
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/external/llvm/utils/TableGen/
DAsmWriterEmitter.cpp403 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]]; in EmitPrintInstruction() local
404 assert(NumOps <= Inst->Operands.size() && in EmitPrintInstruction()
407 Inst->Operands.begin()+NumOps); in EmitPrintInstruction()
738 unsigned NumOps = 0; in CountNumOperands() local
742 ++NumOps; in CountNumOperands()
746 return NumOps; in CountNumOperands()
750 unsigned NumOps = 0; in CountResultNumOperands() local
762 ++NumOps; in CountResultNumOperands()
767 return NumOps; in CountResultNumOperands()
DCodeGenInstruction.cpp71 unsigned NumOps = 1; in CGIOperandList() local
91 NumOps = NumArgs; in CGIOperandList()
116 OperandType, MIOperandNo, NumOps, in CGIOperandList()
118 MIOperandNo += NumOps; in CGIOperandList()
/external/llvm/lib/IR/
DInstruction.cpp24 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps, in Instruction() argument
26 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) { in Instruction()
38 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps, in Instruction() argument
40 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) { in Instruction()
DInstructions.cpp144 unsigned NumOps = e + e / 2; in growOperands() local
145 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common. in growOperands()
150 ReservedSpace = NumOps; in growOperands()
3314 unsigned NumOps = getNumOperands(); in removeCase() local
3318 if (2 + (idx + 1) * 2 != NumOps) { in removeCase()
3319 OL[2 + idx * 2] = OL[NumOps - 2]; in removeCase()
3320 OL[2 + idx * 2 + 1] = OL[NumOps - 1]; in removeCase()
3324 OL[NumOps-2].set(0); in removeCase()
3325 OL[NumOps-2+1].set(0); in removeCase()
3336 NumOperands = NumOps-2; in removeCase()
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/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp460 unsigned NumOps = OldMI->getNumOperands(); in finishConvertToThreeAddress() local
461 for (unsigned I = 1; I < NumOps; ++I) { in finishConvertToThreeAddress()
478 unsigned NumOps = MI->getNumOperands(); in convertToThreeAddress() local
495 for (unsigned I = 2; I < NumOps; ++I) in convertToThreeAddress()
608 unsigned NumOps = MI->getNumExplicitOperands(); in foldMemoryOperandImpl() local
609 if (OpNum == NumOps - 1) { in foldMemoryOperandImpl()

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