| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 123 ; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])
124 ; CHECK-EL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
126 ; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
131 ; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
149 ; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])
150 ; CHECK-EB: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
152 ; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
157 ; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
180 ; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])
181 ; CHECK-EL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
[all …]
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
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| D | XCoreFrameLowering.cpp | 153 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
155 MBB.addLiveIn(XCore::R10); in emitPrologue()
161 unsigned FramePtr = XCore::R10; in emitPrologue()
184 unsigned FramePtr = XCore::R10; in emitEpilogue()
207 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII); in emitEpilogue()
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| D | XCoreRegisterInfo.cpp | 66 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
81 Reserved.set(XCore::R10); in getReservedRegs()
260 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; in getFrameRegister()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 45 case R8: case R9: case R10: case R11: in isARMArea1Register()
56 case R8: case R9: case R10: case R11: in isARMArea2Register()
|
| D | ARMCallingConv.td | 99 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
194 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
201 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
|
| D | HexagonRegisterInfo.td | 74 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
108 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
149 R10, R11, R29, R30, R31)> {
|
| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 36 #define R10 56 macro
|
| /external/valgrind/main/VEX/orig_ppc32/ |
| D | return0.orig | 242 1: PUTL t0, R10
252 7: GETL R10, t6
298 39: GETL R10, t28
327 60: PUTL t46, R10
436 3: GETL R10, t4
441 6: GETL R10, t6
443 8: PUTL t6, R10
525 12: GETL R10, t10
530 15: GETL R10, t12
532 17: PUTL t12, R10
[all …]
|
| D | date.orig | 242 1: PUTL t0, R10
252 7: GETL R10, t6
298 39: GETL R10, t28
327 60: PUTL t46, R10
436 3: GETL R10, t4
441 6: GETL R10, t6
443 8: PUTL t6, R10
525 12: GETL R10, t10
530 15: GETL R10, t12
532 17: PUTL t12, R10
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 572 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
609 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
645 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
681 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
682 return X86::R10; in getX86SubSuperRegister()
|
| D | X86InstrControl.td | 256 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
257 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
258 let Defs = [RAX, R10, R11, RSP, EFLAGS],
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| D | X86CallingConv.td | 202 // The 'nest' parameter, if any, is passed in R10.
203 CCIfNest<CCAssignToReg<[R10]>>,
263 // The 'nest' parameter, if any, is passed in R10.
264 CCIfNest<CCAssignToReg<[R10]>>,
555 def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
|
| D | X86FrameLowering.cpp | 104 X86::R8, X86::R9, X86::R10, X86::R11, 0 in findDeadCallerSavedReg()
1450 allocMBB->addLiveIn(X86::R10); in adjustForSegmentedStacks()
1561 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); in adjustForSegmentedStacks()
1563 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10) in adjustForSegmentedStacks()
1567 MF.getRegInfo().setPhysRegUsed(X86::R10); in adjustForSegmentedStacks()
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 148 SC2(r10,R10); in synth_ucontext()
327 REST(r10,R10); in VG_()
|
| D | sigframe-amd64-linux.c | 347 SC2(r10,R10); in synth_ucontext()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 28 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
50 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 171 ENTRY(R10) \
189 ENTRY(R10) \
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 110 GENOFFSET(AMD64,amd64,R10); in foo()
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 32 def R10 : AMDILReg<10, "r10">, DwarfRegNum<[10]>;
|
| /external/llvm/lib/Target/R600/ |
| D | AMDILRegisterInfo.td | 32 def R10 : AMDILReg<10, "r10">, DwarfRegNum<[10]>;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 32 def R10 : AMDILReg<10, "r10">, DwarfRegNum<[10]>;
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 668 case X86::R8: case X86::R9: case X86::R10: case X86::R11: in isX86_64ExtendedReg()
|
| /external/libvpx/libvpx/third_party/x86inc/ |
| D | x86inc.asm | 404 DECLARE_REG 4, R10, R10D, R10W, R10B, 40
484 DECLARE_REG 7, R10, R10D, R10W, R10B, 16
|